Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Yan, Siao-Cheng; Wu, Chen-Han; Sun, Chong-Jhe; Lin, Yi-Wen; Yao, Yi-Ju; Wu, Yung-Chun

doi:10.3390/nano12132165

Cited by 5 publications

(4 citation statements)

References 24 publications

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“…Fe-FinFETs have been shown to exhibit improved device performance, such as faster switching speeds and reduced power consumption, compared to conventional FinFETs. Among these, Fe-FinFET is a promising option for upcoming applications due to its unique ferroelectric properties [16,17].…”

Section: Introductionmentioning

confidence: 99%

The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET

Zhang

Lin

et al. 2023

Crystals

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In this study, we developed a facilitated ferroelectric high-k/metal-gate n-type FinFET based on Hf0.5Zr0.5O2. We investigated the impact of the hysteresis effect on device characteristics of various fin-widths and the degradation induced by stress on the ferroelectric FinFET (Fe-FinFET). We clarified the electrical characteristics of the device and conducted related reliability inspections. For the Fe-FinFET, the hysteresis behavior of the Hf0.5Zr0.5O2-based gate stack in the Si-fin body is apparent, especially at narrower fin-widths, which affects device performance and reliability under voltage stress. The gate ferroelectric film is worsened after voltage stress with higher impact ionization, resulting in hysteresis degradation and serious induced device performance degradation. It is suggested that the hysteresis degradation is caused by both a shift in polarization of the gate ferroelectric film and generation of interface traps after high-energy carrier stress, which was confirmed by crystal structure inspection.

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Section: Introductionmentioning

confidence: 99%

The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET

Zhang

Lin

et al. 2023

Crystals

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“…This is because the lower the SS value, the greater the change in current, even if the gate voltage is slightly adjusted, the lower the power consumption in the off state. However, the Boltzmann theory states that the basic limit of SS at room temperature is 60 mV/dec, which is a significant barrier to lowering the operating voltage of conventional metal oxide semiconductor field effect transistors (MOSFETs) [ 4 , 5 , 6 , 7 , 8 , 9 ]. Considering the unit of SS value, it means the size of gate voltage required for the drain current value to increase by 10 times.…”

Section: Introductionmentioning

confidence: 99%

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices

et al. 2023

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Hyper-field effect transistors (hyper-FETs) are crucial in the development of low-power logic devices. With the increasing significance of power consumption and energy efficiency, conventional logic devices can no longer achieve the required performance and low-power operation. Next-generation logic devices are designed based on complementary metal-oxide-semiconductor circuits, and the subthreshold swing of existing metal-oxide semiconductor field effect transistors (MOSFETs) cannot be reduced below 60 mV/dec at room temperature owing to the thermionic carrier injection mechanism in the source region. Therefore, new devices must be developed to overcome these limitations. In this study, we present a novel threshold switch (TS) material, which can be applied to logic devices by employing ovonic threshold switch (OTS) materials, failure control of insulator–metal transition materials, and structural optimization. The proposed TS material is connected to a FET device to evaluate its performance. The results demonstrate that commercial transistors connected in series with GeSeTe-based OTS devices exhibit significantly lower subthreshold swing values, high on/off current ratios, and high durability of up to 108.

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“…Although successful scaling down technology is being developed, increase in power density has become an issue due to difficulty in reducing supply voltage (V DD ). Recently, research on overcoming these limitations by achieving a sub-threshold swing (SS) ≤60 mV/dec through devices such as negative capacitance FET (NC-FET) [1] and tunneling FET (T-FET) [2] using nanomaterials is being actively conducted. In addition, a Hybrid-Phase Transition Field-Effects-Transistor (hyper-FET) [3] device utilizing the steep switching characteristic of nano-scale Phase-Transition Materials (PTM) [4,5] has been proposed, and various material and process prospective studies are actively being conducted.…”

Section: Introductionmentioning

confidence: 99%

Hyper-FET’s Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

et al. 2022

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In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by −16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

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Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

Cited by 5 publications

References 24 publications

The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET

The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices

Hyper-FET’s Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

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