As a selection device for highly integrated crossbar‐type data storage, the chalcogenide‐based ovonic threshold switch (OTS) shows high selectivity, fast switching speed, and bi‐directional operation ability for stacking with versatile memory devices. These promising performance features of OTS are based on electronic resistance switching through the amorphous chalcogenide active layer. However, there is a need to improve the thermal stability of the chalcogenide material, which is essential for maintaining the amorphous structure, and the minimization of the operation voltage shift phenomenon, which is essential for achieving sufficient endurance performance. In this study, the active layer of Se‐doped (at 5%) GeTe (SGT) is investigated as a selection device with the potential for high thermal stability (<400 °C) and extreme endurance performance (>1012). The Se introduced into the GeTe (GT) layer compensates for the Te vacancy in the GT layer, making the SGT layer resistant to crystallization in high‐thermal‐budget circumstances. To achieve extremely high endurance performance, a device structural reconfiguration is proposed that minimizes the operation voltage shift by restricting the surge current in its initial resistance switching stage. The results of analyses of the materials and electrical characteristics of the OTS demonstrate its enhanced performance.
A new architecture has become necessary owing to the power consumption and latency problems of the von Neumann architecture. A neuromorphic memory system is a promising candidate for the new system as it has the potential to process large amounts of digital information. A crossbar array (CA), which consists of a selector and a resistor, is the basic building block for the new system. Despite the excellent prospects of crossbar arrays, the biggest obstacle for them is sneak current, which can cause a misreading between the adjacent memory cells, thus resulting in a misoperation in the arrays. The chalcogenide-based ovonic threshold switch (OTS) is a powerful selector with highly nonlinear I–V characteristics that can be used to address the sneak current problem. In this study, we evaluated the electrical characteristics of an OTS with a TiN/GeTe/TiN structure. This device shows nonlinear DC I–V characteristics, an excellent endurance of up to 109 in the burst read measurement, and a stable threshold voltage below 15 mV/dec. In addition, at temperatures below 300 °C, the device exhibits good thermal stability and retains an amorphous structure, which is a strong indication of the aforementioned electrical characteristics.
The immense increase of unstructured data require novel computing systems that can process the input data with low power and parallel processing. This functionality is similar to that of human brains that are composed of numerous neurons, synapses, and their complex connections. To mimic the functionality of the human brain with an electronic device, the resistive switching device and crossbar array has attracted considerable attention for artificial synaptic devices and integrated systems, respectively. For this purpose, the self-rectifying resistive switching cell based on the Si:ZrO x thin film is developed and its reliability characteristics are tested. Four achievements are highlighted in this study. 1) The retention characteristic is improved by the adoption of TaO x thin film as an oxygen reservoir layer. 2) The asymmetric electrodes can make the self-rectifying resistive cell (SRC) have sufficient rectifying characteristic. 3) The linearity of conductance update has a dominant effect on the inference performance compared to that of the conductance range variation. 4) The device of the interface-type resistive switching shows a high enough device yield in the crossbar array device and exhibits reliable multiply-and-accumulate operations in the crossbar array to mimic the human brain-inspired computing system.
TiN/AlOx:Ti/TaOx/TiN memory devices using bilayer resistive switching memory demonstrated excellent durability and capability of QLC (quad-level cell) memory devices. The best nonvolatile memory characteristics with the lowest operation current and optimized 4 bit/cell states were obtained using the Incremental Step Pulse Programming (ISPP) algorithm in array. As a result, a superior QLC reliability (cycle endurance > 1 k at each level of the QLC, data retention > 2 h at 125 °C) for all the 4 bits/cell operations was achieved in sub-μm scaled RRAM (resistive random access memory) devices.
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