Hyper-FET’s Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

Abstract

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by −16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

“…The parameters of PTM used for designing the hybrid-CMOS inverter have been documented in table 2, showing the alterations made from those originally provided in table 1. The parameters follow all the device design-related constraints [3,9]. The circuit design in figure 2 is implemented and simulated in the analog design environment of the cadence tool.…”

“…Once the current begins to decrease and reaches the metallic-to-insulating critical current (I C-MIT ), the material switches back to the metallic state [2]. Considerable research is currently underway to investigate the practicality of phase transition material (PTM) in creating low-power circuits [3]. Notably, recent studies have revealed the potential of employing PTM in designing low-power circuits specifically tailored for medical devices [4].…”

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices

“…This is because the lower the SS value, the greater the change in current, even if the gate voltage is slightly adjusted, the lower the power consumption in the off state. However, the Boltzmann theory states that the basic limit of SS at room temperature is 60 mV/dec, which is a significant barrier to lowering the operating voltage of conventional metal oxide semiconductor field effect transistors (MOSFETs) [ 4 , 5 , 6 , 7 , 8 , 9 ]. Considering the unit of SS value, it means the size of gate voltage required for the drain current value to increase by 10 times.…”