Despite the use of transition metal dichalcogenides being widespread in various applications, the knowledge and applications of MoxW1−xS2 compounds are relatively limited. In this study, we deposited a MoW alloy on a Si substrate using a sputter system. Consequently, we successfully utilized a furnace to sulfurize the MoW alloy from 800 to 950 °C, which transferred the alloy into a MoxW1−xS2 ternary compound. The Raman spectra of the MoxW1−xS2 samples indicated an additional hybridized Raman peak at 375 cm−1 not present in typical MoS2 and WS2. With increasing sulfurization temperature, the scanning electron microscopy images revealed the surface morphology of the MoxW1−xS2 gradually becoming a sheet-like structure. The X-ray diffraction results showed that the crystal structure of the MoxW1−xS2 tended toward a preferable (002) crystal orientation. The I–V results showed that the resistance of MoxW1−xS2 increased when the samples were sulfurized at a higher temperature due to the more porous structures generated within the thin film. Furthermore, a high-temperature coefficient of resistance for the MoxW1−xS2 thin film sulfurized at 950 °C was about −1.633%/K−1. This coefficient of resistance in a MoxW1−xS2 thin film indicates its suitability for use in thermal sensors.
In this study, we developed a facilitated ferroelectric high-k/metal-gate n-type FinFET based on Hf0.5Zr0.5O2. We investigated the impact of the hysteresis effect on device characteristics of various fin-widths and the degradation induced by stress on the ferroelectric FinFET (Fe-FinFET). We clarified the electrical characteristics of the device and conducted related reliability inspections. For the Fe-FinFET, the hysteresis behavior of the Hf0.5Zr0.5O2-based gate stack in the Si-fin body is apparent, especially at narrower fin-widths, which affects device performance and reliability under voltage stress. The gate ferroelectric film is worsened after voltage stress with higher impact ionization, resulting in hysteresis degradation and serious induced device performance degradation. It is suggested that the hysteresis degradation is caused by both a shift in polarization of the gate ferroelectric film and generation of interface traps after high-energy carrier stress, which was confirmed by crystal structure inspection.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.