Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

Abstract

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W eff per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (>10 8), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices. INDEX TERMS Gate all around, junctionless, nanosheet, multi gate, stacked FET.

A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application

“…The spacer near the source is removed so as to combine biomolecules with the cavity easily. The fabrication flow of GAA-NSFET has been reported in [33], [34], and the cavity formation has been demonstrated in [22]. So, according to above-mentioned literatures, the process flow of GAA-NSFET-based biosensor is shown in Fig.…”

Wafer‐Scale Demonstration of MBC‐FET and C‐FET Arrays Based on Two‐Dimensional Semiconductors

“…Meanwhile, suppressing the short channel effect (SCE) and the resulting increase in off‐state leakage current have become the main technical challenges of traditional planar transistors. [ 2 ] Innovative device structures have been developed to solve these problems, including FinFET, [ 3,4 ] gate‐all‐around FET (GAAFET), [ 5–7 ] multi‐bridge channel FET (MBC‐FET), and complementary FET (C‐FET). [ 8–10 ] The enhanced gate controllability of the channel leads to reduced SCEs and current leakage.…”

Large‐Scale Ultrathin Channel Nanosheet‐Stacked CFET Based on CVD 1L MoS2/WSe2

“…[ 4 ] However, when the technology node is further reduced, FinFET faces the scaling limitation of fin width and fin pitch resulting from difficult fabrication process and performance degradation. [ 5 ] Therefore, for nodes beyond the 5 nm regime, [ 6,7 ] nanosheet (NS) [ 8–10 ] and complementary field‐effect transistor (CFET) [ 11–14 ] with superior electrostatics and device performance have been proposed to replace FinFET, as the novel device architectures to meet the demand of a smaller transistor footprint while maintaining high performance. More obviously, the CFET configuration with vertical stacked nFET/pFET can provide further layout area reduction, making itself the most promising candidate for ultrascaling.…”