This paper presents a detailed analysis of the reliability characteristics of Partially-Insulated FinFETs (PI-FinFETs) where a new source / drain structure was adapted using a padPolysilicon Side Contact (PSC). The PSC structure shows excellent improvements in device performances mainly due to the increment of the contact area by using lateral faces of FinFETs. The hot carrier degradation characteristics are also improved in comparison with a conventional source / drain structure having planar contact. This is due to an advantageous impact ionization position. By applying PSC structure to Pi-FinFETs, an optimized source / drain structure of PI-FinFETs can be obtained with its own advantages. [
For the first time, we have successfully fabricated fully integrated advanced bulk FinFETs featuring partially insulating oxide layers under source/drain (S/D), named Partially-Insulated-FinFETs (PI-FinFETs), to control subchannel on the bottom part of the gate in bulk FinFETs and suppress punchthrough and junction leakage currents. We observed that the junction leakage is improved about 50%, Drain-Induced Barrier Lowering (DIBL) about 25%, and lifetime of Hot Carrier Effect (HCE) about 1 order in comparison with normal bulk FinFETs. Furthermore, we propose a novel PI-FinFET structure with pad-Polysilicon Side Contact (PSC) in bulk-Si to reduce Gate Induced Drain Leakage (GIDL) and increase I on with improved SCE immunity. The simulation of novel structure shows that I on , DIBL and GIDL is improved dramatically with the same I off in comparison with bulk FinFETs. This advanced structure is suitable for the miniaturization of GIDL of bulk FinFETs with improved I on , I off and DIBL characteristics.
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