Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond

Abstract

For the first time, we have successfully fabricated fully integrated advanced bulk FinFETs featuring partially insulating oxide layers under source/drain (S/D), named Partially-Insulated-FinFETs (PI-FinFETs), to control subchannel on the bottom part of the gate in bulk FinFETs and suppress punchthrough and junction leakage currents. We observed that the junction leakage is improved about 50%, Drain-Induced Barrier Lowering (DIBL) about 25%, and lifetime of Hot Carrier Effect (HCE) about 1 order in comparison with normal bulk FinFETs. Furthermore, we propose a novel PI-FinFET structure with pad-Polysilicon Side Contact (PSC) in bulk-Si to reduce Gate Induced Drain Leakage (GIDL) and increase I on with improved SCE immunity. The simulation of novel structure shows that I on , DIBL and GIDL is improved dramatically with the same I off in comparison with bulk FinFETs. This advanced structure is suitable for the miniaturization of GIDL of bulk FinFETs with improved I on , I off and DIBL characteristics.

Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer

“…Some outstanding results were reported in those researches that SCE immunities were improved by self-induced halo region and self-limiting S/D shallow junction. The bulk-FinFET implementing partially insulating layers (Pi-FinFET) had also been successfully integrated by merging the bulk-FinFET and PiFET structure [5]. That structure decreased the junction leakage and suppressed the bulk punch through under the vertical finstructure-gates.…”