UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the fi nest patterns.We have been focused on the resolution improvement in NIL template making with a 100keV acceleration voltage spot beam EB writer process, and have established a template making process to meet the requirements of the pioneers. Usually such templates needed just a small fi eld (several hundred microns square or so). Now, for several semiconductor devices, the UV NIL is considered not only as a patterning solution for R&D purpose but eventually as a potential candidate for production, and instead of a small fi eld, a full chip fi eld mask is required. Although the 100kV EB writers have excellent resolution capability, they are adopting spot beams (SB) to generate the pattern and have a fatally low throughput if we need full chip writing.In this paper, we are focusing on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50keV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right Continues on page 3. Historically, many people in semiconductor industry took it for granted that mask making was straight forward. They believed mask making was never a challenge especially when compared to other lithographic technologies. However, next generation lithography (NGL) proved that masks were diffi cult to fabricate. Why? Because NGL masks became one of the main failure reasons of NGLs, such as XPL and EPL, or IPL. The question is whether a similar thing will happen with double patterning (DP) technology and EUV lithography.Double patterning was proposed because it enabled pitch relaxation. Combine pitch relaxation with immersion exposure, and 32-and 22-nm technology nodes seem achievable. Resolution is improved but now the real challenges are transferred to mask making process. When we use one mask to execute the exposure, we require good CD uniformity on the mask. However, when we use two masks to generate one pattern (as with double patterning) we need to control the combined CD of a pair of double-patterning masks; which requires perfect CD Mean to Target (MTT) from the pair DP masks. For example, ITRS requires the difference in CD MTT of two DP masks be smaller than 1.3 nm and 0.9 nm for 32 and 22 nm, respectively.A current mask fabrication tool set would include a 50 kV e-beam writer, a ICP-bias power plasma etcher, a deep UV inspection tool, a FIB repair tool, and wet-megasonic cleaning tool. These confi gurations have been used for both 130nm and 90-nm technology nodes. Improvements have been made gradually for every technology node, but there has been no revolutionary progress. The question is: How far can these confi gurations go? Can these tool sets be used for 32-and 22-nm technology nodes?Let's break down the CD MTT budgets of mask fabrication processes which affect the fi nal CD values on the masks. For e-beam exposure, the dose is the mo...

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EUV mask pattern inspection was investigated using current DUV reticle inspection tool. Designed defect pattern of 65nm node and 45nm node were prepared. We compared inspection sensitivity between before buffer etch pattern and after buffer etch pattern, and between die to die mode and die to database mode. Inspection sensitivity difference was not observed between before buffer etch pattern and after buffer etch pattern. In addition to defect inspection, wafer print simulation of program defect was investigated. Simulation results were compared to inspection result. We confirmed current DUV reticle inspection tool has potential for EUV mask defect inspection.

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Nano-imprint lithography (NIL) has been counted as one of the lithography solutions for hp32nm node and beyond.Recently, the small line edge roughness (LER) as well as the potentially high resolution that will ensure no-OPC mask feature is attracting many researchers. The template making is one of the most critical issues for the realization of NIL. Especially when we think of a practical template fabrication process on a 65mm square format that is going to be the industry standard, the resolution of the template making process showed a limitation. We have achieved for the first time an hp22nm resolution on the 65nm template format. Both line and space patterns and hole patterns were well resolved. Regarding dot patterns, we still need improvement, but we have achieved resolution down to hp28nm. Although so far we cannot achieve these resolution limits of various pattern category at the same time on one substrate, an intermediate process condition showed sufficient uniformity both in lateral CD and in vertical depth. Global pattern image placement also showed sufficient numbers at this stage of lithography development. A 20nm feature (with a pitch of 80nm) showed sufficient imprint result.

Nano-imprint lithography (NIL) has been counted as one of the lithography candidates for hp32nm node and beyond and has showed excellent resolution capability with remarkable low line edge roughness that is attracting many researchers in the industry who were searching for the finest patterning technology. Therefore, recently we have been focusing on the resolution improvement on the NIL templates with the 100keV acceleration voltage spot beam (SB) EB writer and the 50keV acceleration voltage variable shaped beam (VSB) EB writer.The 100keV SB writers have high resolution capability, but they show fatally low throughput if we need full chip writing. Usually templates for resolution pioneers needed just a small field (several hundred microns square or so), but recently requirements for full chip templates are increasing. For full chip writing, we have also started the resolution improvement with the 50keV VSB writers used in current 4X photomask manufacturing. The 50keV VSB writers could generate full chip pattern in a reasonable time though resolution limits are inferior to that with the 100keV SB writers.In this paper, we will show latest results with both the 100keV SB and the 50keV VSB EB writers. With the 100keV SB EB writer, we have achieved down to hp15nm resolution for line and space pattern, but found that to achieve further improvement, an innovation in pattern generation method or material would be inevitable. With the 50keV VSB EB writer, we have achieved down to hp22nm resolution for line and space pattern.Though NIL has excellent resolution capability, solutions for defect inspection and repair are not clearly shown yet. In this paper, we will show preliminary inspection results with an EB inspection tool. We tested an EB inspection tool by Hermes Microvision, Inc. (HMI), which was originally developed for and are currently used as a wafer inspection tool, and now have been started to seek the application for mask use, using a programmed defect template.