BACKGROUND Long-term trends of the incidence and outcome of cardiogenic shock (CS) patients are scarce. We analyze for the first time trends in the incidence and outcome of CS during a 20-year period in Switzerland. METHODS AND RESULTS The AMIS (Acute Myocardial Infarction in Switzerland) Plus Registry enrolls patients with acute myocardial infarction from 83 hospitals in Switzerland. We analyzed trends in the incidence, treatment, and in-hospital mortality of patients with CS enrolled between 1997 and 2017. The impact of revascularization strategy on outcome was assessed for the time period 2005 to 2017. Among 52 808 patients enrolled, 963 patients were excluded because of missing data and 51 842 (98%) patients remained for the purpose of the present analysis. Overall, 4090 patients (7.9%) with a mean age of 69.6±12.5 years experienced acute myocardial infarction complicated by CS. Overall, rates of CS declined from 8.

BackgroundOn September 27, 2012, at 3:43 pm, a hydrogen fluoride spill occurred in a manufacturing plant located at the 4th complex of the Gumi National Industrial Complex in Gumi City, South Korea. The present study aimed to evaluate the psychological effects of the hydrogen fluoride spill on the members of the community and to investigate their relationships with physical symptoms and changes in psychological effects occurring as time passed after the accident.MethodsThe 1st phase involved a survey of 1359 individuals that was conducted 1 month after the spill, and the 2nd phase involved a survey of 711 individuals that was conducted 7 months after the accident. The questionnaires included items for assessing demographic characteristics, hydrogen fluoride exposure level, physical symptoms, and psychological status. Physical symptoms were assessed to determine the persistence of irritations. Psychological status was assessed to investigate the impact of event level using the Impact of Event Scale – Revised Korean version (IES-R-K), and the anxiety level was assessed using the Beck Anxiety Inventory (BAI).ResultsAs the hydrogen fluoride exposure level increased, the impact of event and anxiety levels increased significantly both 1 and 7 months after the accident (p < 0.05). The mean score of the impact of event levels decreased significantly from 33.33 ± 14.64 at 1 month after the accident to 28.68 ± 11.80 at 7 months after the accident (p < 0.05). The mean score of the anxiety levels increased significantly from 5.16 ± 6.59 at 1 month after the accident to 6.79 ± 8.41 at 7 months after the accident (p < 0.05). The risk of persistent physical symptoms at 7 months after the accident was significantly higher in females. The risk of persistent physical symptoms also increased significantly, with increasing age, hydrogen fluoride exposure, and impact of event levels (p < 0.05).ConclusionsThe present study found that the impact of event level and anxiety level increased with increasing hydrogen fluoride exposure. Anxiety levels persisted even after time passed. The risk of persistent physical symptoms at 7 months after the accident was higher in females, and it increased with increasing age, hydrogen fluoride exposure level, and impact of event levels.

An activated carbon adsorption model was developed to predict final permeate concentrations of a target trace organic compound (o-dichlorobenzene, DCB) under the variable influent concentration in powdered activated carbon-ultrafiltration (PAC-UF) system for drinking water production. The results were then compared with experimental DCB concentrations both in bulk and permeate. In the adsorption period, the DCB concentrations both in bulk and permeate were always lower than the predicted ones while the permeate concentrations were lower than the bulk ones regardless of membrane materials used and PAC doses. On the other hand, during the desorption period, the experimental values were higher or lower than the predicted ones depending on PAC dose and membrane used. The competitive adsorption and/or desorption of DCB between PAC and membrane itself resulted in this discrepancy, and this trend was more pronounced in a hydrophobic membrane.

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Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require costeffective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement. Figure 11.8.1 shows the micrograph and device feature of the 64Gb 3b/cell DDR NAND flash memory chip, fabricated in 20nm-node CMOS technology. The chip has two 32Gb memory planes. Each plane consists of 2732 blocks with 8KB page size and 1.5MB block size. The block consists of 64-cell strings with 2-dummy WLs to reduce NAND string overhead and abnormal disturbance [2]. To realize a small die area with 65.3% cell efficiency and 200Mb/s high-speed DDR interface in the 3b/cell NAND chip, a one-sided page buffer structure, 2-way interleaving and 2-stage pipeline architecture [3] are used. To further reduce chip size, a shared block decoder scheme is used, as shown in Fig. 11.8.2. Compared to a conventional block decoder where every block's WLs transfer gates have their own block decoder circuit [4], two different block WLs transfer gates are shared with single block decoder in this chip. By selecting the drive lines of WLs transfer gate, only the WLs of selected memory array are driven. Using the shared block decoder scheme reduces the row-decoder area by 25%, which results in 4.2% chip size reduction. In addition to that, 30% pump area reduction is also achieved because that total output loading of pump circuits is reduced compared to the conventional scheme. The results in a further 0.3% chip-size reduction. With simple bad-block-remapping logic in peripheral circuits, conventional bad-block replacement can be fully supported.Controlling V th distribution without performance degradation in 3b/cell NAND chip is a critical challenge at the 20nm-node. A 2-step verify ISPP scheme of programming [5] is helps to achieve a tighter V th distribution width than that of conventional ISPP programming [6] that is used widely in MLC NAND flash. As shown in Fig. 11.8.3, the BL voltage of a programmed cell is raised from 0V to a predetermined low voltage during 1st step verify, which is slighty lower than the target verify level. Because it suppresses FN tunneling current at programming, it slows down a rate of V th shift, realizing a tighter V th distribution compared to the conventional ISPP scheme. The 2-step verify ISPP scheme, however, requires two times more verify operations for each target V th state, causing an increase in program time. This is especially true for 3b/cell N...

SUMMARYIn this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 × 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.

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We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.