A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

Shin, Seung-Hwan; Shim, Dong-Kyo; Jeong, Junho; Kwon, O.H.; Yoon, Seong Yong; Choi, Minsuk; Kim, Tae‐Young; Park, Hyun-Wook; Yoon, Hyun-Jun; Song, Young-Jae; Choi, Yoon-Hee; Shim, Sang-Won; Ahn, Y. H.; Park, Kitae; Han, Jin-Man; Kyung, Kye-Hyun; Jun, Young-Hyun

doi:10.1109/vlsic.2012.6243825

Cited by 27 publications

(7 citation statements)

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“…This occurs because MSB programming can only increase (and not reduce) the threshold voltage of the cell from its partially-programmed voltage (and thus cannot move a multi-level cell that should be in the P3 state into the ER state, or one that should be in the P2 state into the P1 state). TLC NAND flash is much less susceptible to program errors than MLC NAND flash, as the data read from the SLC buffers in TLC NAND flash has a much lower error rate than data read from a partially-programmed MLC NAND flash wordline [167].…”

Section: Program Errors Lsb Should Be 1 But Is Incorrectly Programmed Tomentioning

confidence: 99%

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

et al. 2017

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NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: (1) effective process technology scaling; and (2) multi-level (e.g., MLC, TLC) cell data coding. Unfortunately, the reliability of raw data stored in flash memory has also continued to become more difficult to ensure, because these two trends lead to (1) fewer electrons in the flash memory cell floating gate to represent the data; and (2) larger cell-to-cell interference and disturbance effects. Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory. As a result, flash memory controllers in solid-state drives (SSDs) have become much more sophisticated: they incorporate many effective techniques to ensure the correct interpretation of noisy data stored in flash memory cells. In this article, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. We provide rigorous experimental data from state-ofthe-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several mitigation and recovery techniques, including (1) cell-to-cell interference mitigation; (2) optimal multi-level cell sensing; (3) error correction using state-of-the-art algorithms and methods; and (4) data recovery when error correction fails. We quantify the reliability improvement provided by each of these techniques. Looking forward, we briefly discuss how flash memory and these techniques could evolve into the future.

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Section: Program Errors Lsb Should Be 1 But Is Incorrectly Programmed Tomentioning

confidence: 99%

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

et al. 2017

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“…In the MLC and TLC architectures the write throughput is smaller than the read throughput (see Table I). In fact, to lower the RBER retrieved during read operations, sophisticated but long program algorithms are used [2], [29]. To deal with this bandwidth mismatch, it is usual to leverage multi-plane program commands which allow writing, on the same memory die, two or more pages in the time-frame of a single page program.…”

Section: B Realistic Workloads -Enterprise and Consumer Hostsmentioning

confidence: 99%

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

Zuolo

Zambelli

Marelli³

et al. 2019

IEEE Trans. Emerg. Topics Comput.

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The reliability of non-volatile NAND flash memories is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it is essential to exploit powerful correction algorithms such as the Low Density Parity Check. However, the burdens of this approach materialize in a disk performance reduction. In this work a standard decoding approach is compared with an optimized solution exploiting hardware resources available in NAND flash chips. The simulation results on 2X, 1X and mid-1X MLC and TLC NAND flashbased Solid State Drives in terms of disk bandwidth, average latency, and Quality of Service favor the adoption of the presented solution in different host scenarios and realistic workloads. The proposed solution is particularly effective when high error correction interventions and read-or write-intensive workloads are considered.

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“…As a result, it not only lengthens the program time, due to multiple shots, but also results in the tail bit problem, i.e., more disturbance to cells of the leftmost distribution in threshold voltages, due to a number of program iterations. While very little work was done in this direction, the most related ones are those that tried to improve the reliability of MLC chips [5,15,18]: In particular, a sequential programming style was proposed to program cells of the lowest threshold voltage to ones of the highest one to avoid applying the same program voltages repeatedly for each logical state [15]. With the considerations of the disturbance effects, a coarse-grained step was proposed to program cells at the first run and then to go back with a finegrained step to re-program a cell to its target voltage after its adjacent pages have been programmed [18].…”

Section: D (3d) Flash Memory Chips Memory Technology Device Layer (Mtd)mentioning

confidence: 99%

Achieving SLC performance with MLC flash memory

Chang

Kuo

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Although the Multi-Level-Cell technique is widely adopted by flashmemory vendors to boost the chip density and to lower the cost, it results in serious performance and reliability problems. Different from the past work, a new cell programming method is proposed to not only significantly improve the chip performance but also reduce the potential bit error rate. In particular, a Single-Level-Cell-like programming style is proposed to better explore the threshold-voltage relationship to denote different Multi-Level-Cell bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in Single-Level-Cell chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming style could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for Multi-Level-Cell pages.

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A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

Cited by 27 publications

References 1 publication

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

Achieving SLC performance with MLC flash memory

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