LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

Zuolo, Lorenzo; Zambelli, Cristian; Marelli, Alessia; Micheloni, Rino; Olivo, P.

doi:10.1109/tetc.2017.2688079

Cited by 18 publications

(10 citation statements)

References 13 publications

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“…Over GF (2), LLRBP [10], SBP [11] and QABP [17] algorithms are performed for comparison with the proposed VNBP-MP algorithm. In addition, FFT-BP [25] and FFT-SBP [26] algorithms are used for comparison with the NVNBP-MP algorithm over GF (4). The above two algorithms, which exploit fast fourier transform to reduce the computation complexity, are non-binary versions of the LLRBP and SBP algorithms.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…In the simulation of the MLC NAND flash channel model, we exploit non-binary LDPC codes [24] con- structed over GF (4). Each quaternary symbol represents the value '0', '1', '2' or '3'.…”

Section: B Nvnbp-mp Decoding Algorithm For Non-binary Ldpc Codesmentioning

confidence: 99%

“…The classification only depends on the region where a specified cell lies. As stated before, the definition of the blurry variable node over GF (4) is different from that over GF (2).…”

Section: B Nvnbp-mp Decoding Algorithm For Non-binary Ldpc Codesmentioning

confidence: 99%

“…into four types: single-level cell (SLC, 1bit/cell), multi-level cell (MLC, 2bits/cell), triple-level cell (TLC, 3bits/cell) and quad-level cell (QLC, 4bits/cell) [3], [4].…”

Section: Introductionmentioning

confidence: 99%

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Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory

2019

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With the fast development of non-volatile storage technology, NAND flash memory faces more and more challenges such as data reliability and lifetime. To overcome the issue of the reliability, low-density parity-check (LDPC) codes are considered as a main candidate of error-correction-codes (ECCs) for NAND flash storages. However, conventional soft decoding algorithms for LDPC codes suffer from the drawback of slow convergence speed, which increases the decoding latency. For achieving fast convergence speed, a variable-node-based belief-propagation with message pre-processing (VNBP-MP) decoding algorithm for binary LDPC codes and a non-binary VNBP-MP (NVNBP-MP) decoding algorithm for non-binary LDPC codes are proposed. Both of the algorithms utilize the characteristics of the NAND flash channel to perform the message pre-processing operations. In theory, the propagation of unreliable messages can be effectively prevented and the propagation of reliable messages can be speeded up. To further improve the decoding convergence, the treatment for oscillating variable nodes is considered after the message pre-processing operations. The simulation results also show that the proposed algorithms both have a noticeable improvement in convergence speed and latency, without compromising error-correction performance, compared with the existing soft decoding algorithms. INDEX TERMS NAND flash memory, low-density parity-check (LDPC) code, message pre-processing, belief-propagation decoding, error-correction performance.

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Section: Simulation Resultsmentioning

confidence: 99%

“…In the simulation of the MLC NAND flash channel model, we exploit non-binary LDPC codes [24] con- structed over GF (4). Each quaternary symbol represents the value '0', '1', '2' or '3'.…”

Section: B Nvnbp-mp Decoding Algorithm For Non-binary Ldpc Codesmentioning

confidence: 99%

“…The classification only depends on the region where a specified cell lies. As stated before, the definition of the blurry variable node over GF (4) is different from that over GF (2).…”

Section: B Nvnbp-mp Decoding Algorithm For Non-binary Ldpc Codesmentioning

confidence: 99%

“…into four types: single-level cell (SLC, 1bit/cell), multi-level cell (MLC, 2bits/cell), triple-level cell (TLC, 3bits/cell) and quad-level cell (QLC, 4bits/cell) [3], [4].…”

Section: Introductionmentioning

confidence: 99%

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Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory

2019

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“…7) We do not observe any relation between I/O error and dead device failures with workload characteristics. 10. Workload dependency represents how different types of SSD failures are affected by different workload characteristics.…”

Section: Failure Characterization Of I/o Caches In Enterprise Storagementioning

confidence: 99%

Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems

Ahmadian

Taheri

Asadi

2021

IEEE Trans. Emerg. Topics Comput.

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I/O caching techniques are widely employed in enterprise storage systems in order to enhance performance of I/O intensive applications in large-scale data centers. Due to higher performance compared to Hard Disk Drives (HDDs) and lower price and nonvolatility compared to Dynamic Random-Access Memories (DRAM), Flash-based Solid-State Drives (SSDs) are used as a main media in the caching layer of storage systems. Although SSDs are known as non-volatile devices but recent studies have reported large number of data failures due to power outage in SSDs. To overcome the reliability implications of SSD-based I/O caching schemes, RAID-1 (mirrored) configuration is commonly used to avoid data loss due to uncommitted write operations. Such configuration, however, may still experience data loss in the cache layer due to correlated failures in SSDs. To our knowledge, none of previous studies have investigated the reliability of SSD-based I/O caching schemes in enterprise storage systems.In this paper, we present a comprehensive analysis investigating the reliability of SSD-based I/O caching architectures used in enterprise storage systems under power failure and high-operating temperature. We explore variety of SSDs from top vendors and investigate the cache reliability in mirrored configuration. To this end, we first develop a physical fault injection and failure detection platform and then investigate the impact of workload dependent parameters on the reliability of I/O cache in the presence of two common failure types in data centers, power outage and high temperature faults. We implement an I/O cache scheme using an open-source I/O cache module in Linux operating system. The experimental results obtained by conducting more than twenty thousand of physical fault injections on the implemented I/O cache with different write policies reveal that the failure rate of the I/O cache is significantly affected by workload dependent parameters. Our results show that unlike workload requests access pattern, the other workload dependent parameters such as request size, Working Set Size (WSS), and sequence of the accesses have considerable impact on the I/O cache failure rate. We observe a significant growth in the failure rate in the workloads by decreasing the size of the requests (by more than 14X). Furthermore, we observe that in addition to writes, the read accesses to the I/O cache are subjected to failure in presence of sudden power outage (the failure mainly occurs during promoting data to the cache). In addition, we observe that I/O cache experiences no data failure upon high temperature faults.

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