Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

Cai, Yu; Ghose, Saugata; Haratsch, Erich F.; Luo, Yi; Mutlu, Onur

doi:10.1109/jproc.2017.2713127

Cited by 232 publications

(179 citation statements)

References 145 publications

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“…This variation leads to new opportunities for correctly recovering data from a flash device that has experienced an uncorrectable error: by identifying which cells are fast-leaking and which cells are slow-leaking, one can probabilistically estimate the original values of the cells before the uncorrectable error occurred. This mechanism, called Retention Failure Recovery, leads to significant reductions in bit error rate in modern MLC NAND flash memory [50,52,53] and is thus very promising. Unfortunately, it also points to a potential security and privacy vulnerability: by analyzing data and cell properties of a failed device, one can potentially recover the original data.…”

Section: Dram Data Retention Issuesmentioning

confidence: 99%

“…In particular, three PhD theses have shaped the understanding that led to this work. These are Yoongu Kim's thesis entitled "Architectural Techniques to Enhance DRAM Scaling" [132], Yu Cai's thesis entitled "NAND Flash Memory: Characterization, Analysis, Modeling and Mechanisms" [49] and his continued follow-on work after his thesis, summarized in [52,53], and Donghyuk Lee's thesis entitled "Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity" [145]. We also acknowledge various funding agencies (NSF, SRC, ISTC, CyLab) and industrial partners (AliBaba, AMD, Google, Facebook, HP Labs, Huawei, IBM, Intel, Microsoft, Nvidia, Oracle, Qualcomm, Rambus, Samsung, Seagate, VMware) who have supported the presented and other related work in our group generously over the years.…”

Section: Acknowledgmentsmentioning

confidence: 99%

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RowHammer: A Retrospective

Mutlu

Kim

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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136

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This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 conference [133]. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically-adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology.Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this article, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or Phase Change Memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities.

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Section: Dram Data Retention Issuesmentioning

confidence: 99%

Section: Acknowledgmentsmentioning

confidence: 99%

RowHammer: A Retrospective

Mutlu

Kim

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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136

125

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“…3) LDPC Code-Specific Optimization of the Read Thresholds : With the above proposed mappings, the SDD of ECCs can then be performed. In this work, we consider the LDPC codes, which have already been widely applied to MLC flash memory channels [1]. Hence the above proposed integerbased reliability measure can be fed into the decoder of the LDPC codes.…”

Section: ) Integer-based Reliability Mappingsmentioning

confidence: 99%

Deep Learning-Aided Dynamic Read Thresholds Design for Multi-Level-Cell Flash Memories

Mei

Cai

2020

IEEE Trans. Commun.

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The practical NAND flash memory suffers from various non-stationary noises that are difficult to be predicted. Furthermore, the data retention noise induced channel offset is unknown during the readback process. This severely affects the data recovery from the memory cell. In this paper, we first propose a novel recurrent neural network (RNN)-based detector to effectively detect the data symbols stored in the multi-levelcell (MLC) flash memory without any prior knowledge of the channel. However, compared with the conventional threshold detector, the proposed RNN detector introduces much longer read latency and more power consumption. To tackle this problem, we further propose an RNN-aided (RNNA) dynamic threshold detector, whose detection thresholds can be derived based on the outputs of the RNN detector. We thus only need to activate the RNN detector periodically when the system is idle. Moreover, to enable soft-decision decoding of error-correction codes, we first show how to obtain more read thresholds based on the hard-decision read thresholds derived from the RNN detector. We then propose integer-based reliability mappings based on the designed read thresholds, which can generate the soft information of the channel. Finally, we propose to apply density evolution (DE) combined with differential evolution algorithm to optimize the read thresholds for LDPC coded flash memory channels. Computer simulation results demonstrate the effectiveness of our RNNA dynamic read thresholds design, for both the uncoded and LDPC-coded flash memory channels, without any prior knowledge of the channel.

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“…OLID-state drives (SSDs) based on NAND flash memory have become popular in consumer electronic devices such as smart phones, tablet and desktop systems [1][2]. It is highly desirable to reduce the amount of data in SSDs and the read/write data transmission time to/from SSDs as flash memory has a finite number of program-erase (P/E) cycles thus limited lifetime [3].…”

Section: Introductionmentioning

confidence: 99%

“…It is highly desirable to reduce the amount of data in SSDs and the read/write data transmission time to/from SSDs as flash memory has a finite number of program-erase (P/E) cycles thus limited lifetime [3]. For example, older single-level cell (SLC) NAND-flash memory was able to withstand 150,000 P/E cycles, while multi-level cell (MLC) NAND-flash memory using 15-19nm process technologies wears out after only 3,000 P/E cycles [2], [4]. Furthermore, the performance of MLC flash memory is also much slower than that of its SLC counterpart.…”

Section: Introductionmentioning

confidence: 99%