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Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require costeffective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement. Figure 11.8.1 shows the micrograph and device feature of the 64Gb 3b/cell DDR NAND flash memory chip, fabricated in 20nm-node CMOS technology. The chip has two 32Gb memory planes. Each plane consists of 2732 blocks with 8KB page size and 1.5MB block size. The block consists of 64-cell strings with 2-dummy WLs to reduce NAND string overhead and abnormal disturbance [2]. To realize a small die area with 65.3% cell efficiency and 200Mb/s high-speed DDR interface in the 3b/cell NAND chip, a one-sided page buffer structure, 2-way interleaving and 2-stage pipeline architecture [3] are used. To further reduce chip size, a shared block decoder scheme is used, as shown in Fig. 11.8.2. Compared to a conventional block decoder where every block's WLs transfer gates have their own block decoder circuit [4], two different block WLs transfer gates are shared with single block decoder in this chip. By selecting the drive lines of WLs transfer gate, only the WLs of selected memory array are driven. Using the shared block decoder scheme reduces the row-decoder area by 25%, which results in 4.2% chip size reduction. In addition to that, 30% pump area reduction is also achieved because that total output loading of pump circuits is reduced compared to the conventional scheme. The results in a further 0.3% chip-size reduction. With simple bad-block-remapping logic in peripheral circuits, conventional bad-block replacement can be fully supported.Controlling V th distribution without performance degradation in 3b/cell NAND chip is a critical challenge at the 20nm-node. A 2-step verify ISPP scheme of programming [5] is helps to achieve a tighter V th distribution width than that of conventional ISPP programming [6] that is used widely in MLC NAND flash. As shown in Fig. 11.8.3, the BL voltage of a programmed cell is raised from 0V to a predetermined low voltage during 1st step verify, which is slighty lower than the target verify level. Because it suppresses FN tunneling current at programming, it slows down a rate of V th shift, realizing a tighter V th distribution compared to the conventional ISPP scheme. The 2-step verify ISPP scheme, however, requires two times more verify operations for each target V th state, causing an increase in program time. This is especially true for 3b/cell N...