Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…In the following, we will review the reliability issues in 3D NAND within the same framework adopted so far: we will only discuss issues that become relevant with P/E cycling or repetitive data read, neglecting those associated, for example, with V T placement, string resistance and time-0 variability. Figure 35 shows the endurance performance of a 3D NAND cell as a function of N C [286] and the V T distribution for a NAND array after heavy cycling [22]. Because of the larger cell size, 3D NAND are reported to have better endurance properties with respect to their planar counterpart, as also claimed in [293][294][295][296], where an endurance of 5-7 k P/E cycles is reported for a TLC 3D NAND.…”

“…Such a device was shown to exhibit superior performance with respect to a conventional vertical nanowire transistor, because of the high defectivity in the central region that plagued the performance of the latter structure. The gate stack of today's 3D NAND can be based on either a floating gate [23,[287][288][289][290][291], similar to planar NAND devices, or a charge-trap stack similar to an oxide/nitride/oxide (ONO) layer, where the charge is stored in traps within the nitride layer [10,11,22,292].…”

“…Unfortunately, the very limited amount of data publicly available makes it hard to conduct an exhaustive assessment of the role played by each of them. On a general standpoint, the 3D cylindrical cell footprint and channel length can be made larger than their planar counterparts [22,291], as the 3D architecture relieves the burden of scaling the cell area by placing it onto the increase in the number of stacked layers. As a consequence, a better reliability is achieved in 3D NAND cells, which resulted in the development of QLCs.…”

“…In this field, a pioneering proposal was put forward in 2001 [16], evolving into early proposals based on layer stacking [17][18][19] and reaching the first cost-effective solution of a 3D-integrated array in 2007 [20]. From there on, 3D NAND based on vertical channels have taken the lead in the quest for higher density, resulting in the first commercial product in 2013 [21,22] and reaching a capacity of 786 Gb with a density of 4.29 Gb/mm 2 [23] while stacking up to 64 layers [23][24][25]. Chip capacity was boosted not only by 3D integration, but also by multi-bit storage: while two bit-per-cell (i.e., multi-level cells, MLCs) were used in the first prototype [21], today's technology relies on storing three bit-per-cell (triple-level cells or TLCs) and quadruple-level cells (QLCs) are under active development.…”

Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory

“…The endurance might need to spend several thousands of hours for practical testing of a single NAND device around 2019 [5]. This testing time is going to continuously increase due to the appearance of the high capacity three dimensional flash devices [6,7] beyond the two dimensional process. Consequently, the test cost associated with the increase in testing time could be the most important factor for the device cost [8][9][10].…”