2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers 2015
DOI: 10.1109/isscc.2015.7062960
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7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

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Cited by 57 publications
(29 citation statements)
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“…Figure 35 shows the endurance performance of a 3D NAND cell as a function of N C [286] and the V T distribution for a NAND array after heavy cycling [22]. Because of the larger cell size, 3D NAND are reported to have better endurance properties with respect to their planar counterpart, as also claimed in [293][294][295][296], where an endurance of 5-7 k P/E cycles is reported for a TLC 3D NAND. All these cells feature an ONO stack.…”
Section: D Nand Reliabilitymentioning
confidence: 57%
“…Figure 35 shows the endurance performance of a 3D NAND cell as a function of N C [286] and the V T distribution for a NAND array after heavy cycling [22]. Because of the larger cell size, 3D NAND are reported to have better endurance properties with respect to their planar counterpart, as also claimed in [293][294][295][296], where an endurance of 5-7 k P/E cycles is reported for a TLC 3D NAND. All these cells feature an ONO stack.…”
Section: D Nand Reliabilitymentioning
confidence: 57%
“…The second V-NAND generation has been introduced in 2015 by increasing the storage bit density from two bits/cell to three bits/cell [12]. Comparing with the previous generation, there were not many macroscopic changes in the memory cell structure, although the number of layers switched from 24 to 32.…”
Section: V-nand Architecturementioning
confidence: 99%
“…The bitlines layout is different as sketched in Figure 23. In this case, two bitlines are arranged in a single pillar pitch [12]. BL density is doubled (i.e., the NAND Flash page size step from 8 kB to 16 kB), but the number of contacts to the SL plate is halved.…”
Section: V-nand Architecturementioning
confidence: 99%
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“…Since 3D NAND Flash has come to market in 2014 [1], the memory array size has been nearly doubled every year [2,3,4]. The increasing density of 3D NAND flash array causes the increasing parasitic capacitance of word lines (WLs).…”
Section: Introductionmentioning
confidence: 99%