A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology

Wordline (WL) voltage-generating system is a crucial block in flash memory. It generates a voltage higher than the supply voltage for reading, programming and erasing in flash memory. However, operation accuracy is deteriorated by the excessive overshoot and ripple voltage. Moreover, current consumption in standby mode shortens the life of memory. The paper presents a high-performance wordline voltagegenerating system in 55nm CMOS technology. In active mode, a variable stage and frequency charge pump system is proposed to suppress overshoot and ripple of WL voltage (VWL) when the supply voltage ranges from 1.5 V to 2.1 V. To cut down standby current, an ultra-low power voltage reference circuit operating in subthreshold region is introduced. When recovering from standby mode, a standby recovery management circuit is utilized to minimize WL voltage setup time. The ripple voltage is 3 mV at 30 pF load with 20 MHz pumping frequency in active mode in post-simulation. The WL voltage setup time when recovery from standby mode is equal to 13.7 ns, even though the average standby current is less than 0.98 μA typically.

Section: Introductionmentioning

confidence: 99%

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Zhou

Yan

Ming

2023

“…High-performance CP design is another challenge under the low voltage supply, the reference spur is mainly induced by the non-ideal effects of CP and phase and frequency detector (PFD) circuit. In general, the cascode operation amplifier and negative feedback technique are used to guarantee the charging and discharging current matching in the conventional charge pump circuit [16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]. However, the threshold voltage does not decrease with the voltage supply [30], resulting in the efficient operating voltage range of the charge pump becoming narrower.…”

Section: Introductionmentioning

confidence: 99%

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

Chen

2022

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ∆Σ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves −85.94 dBc/Hz@100 kHz and −109.18 dBc/Hz@1 MHz in fractional-N mode while consuming 1.6 mW under a 0.7 V voltage supply.

“…As a result, the advanced pump structures with smaller size and higher efficiency have been extensively researched [10,11,12,13,14,15,16,17,18,19]. Meanwhile more attentions are paid to the regulation techniques [20,21,22,23,24,25] or the clock inputs [26,27,28,29,30,31] of charge pumps, since the regulation and clocking schemes have also become more and more crucial to reduce power and chip size of pump system [4,22].…”

Section: Introductionmentioning

confidence: 99%

A charge pump system with new regulation and clocking scheme

Zhu

Jiang

Lin

et al. 2019

A novel charge pump system with new regulation and clock generating techniques is proposed and verified in a 0.13 µm CMOS process. Rather than generating the reference voltage by band-gap reference (BGR) and the detected voltage by high voltage divider in the conventional regulation, both voltage reference and division of proposed pump system are implemented by single new circuit. Besides, the conventional oscillator for clock input of charge pump system is removed while an adaptive clock generation scheme is introduced to reduce the power consumption and shrink the system size. The experiment results show that the pump system can produce a stable and smooth output with a small ripple, and the high output accuracy is comparable to the conventional solution equipped with BGR. Moreover, the power consumption of the pump controlling is reduced by about 80% while the size of pump system is decreased by about 25%. Therefore, the proposed regulated charge pump (RCP) is very suitable for ultra-low power and high precision applications, for example, the embedded nonvolatile memories (eNVMs).