A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

Abstract

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ∆Σ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves −85.94 dBc/Hz@100 kHz and −109.18 dBc/Hz@1 MHz in fractional-N mode while consuming 1.6 mW under a 0.7 V voltage supply.

Multi-chip phase synchronization circuit of fractional-N PLL

“…When the phase deviation between the local oscillators or the clock signals in different transceivers is too large, the signal-to-noise ratio and communication quality will decrease, and even directly lead to the failure of beamforming in the phased array radar system [11,12]. Frequency synthesizer based on fractional-N PLL [13,14] is often used to generate local oscillator signal or system clock [15,16] in transceiver chip because of its high frequency resolution [17,18,19]. However, due to the phase randomness between the output codewords of sigma-delta modulator(SDM) [20,21,22] in different fractional-N PLLs, the phase relationship between the output signals of PLL after each lock is uncertain even if the same reference frequency is input.…”