With the CMOS technology scaling down, the normal latch is more susceptible to soft errors caused by radiation particles. In this paper, we proposed a low-power and highly reliable radiation hardened latch to enhance the single event upset (SEU) tolerance. Based on DICE latch and Muller C-element circuit, the proposed latch can provide 100% fault tolerance, which can be used for space applications in severe ray radiation environments. The simulation show that's it not only can completely tolerate an SEU on any one of its internal single node, but it also can provide doublenode and triple-node upsets protection for facultative initial state of the latch. What's more, compared with other hardened latches, the proposed cell has comparable or better performance in the matter of delay time and power.

In this paper, an improved SEU hardened SRAM bit-cell, based on the SEU physics mechanism and reasonable circuit-design, is proposed. The proposed SRAM cell can offer differential read operation for robust sensing. By using 90 nm standard digital CMOS technology, the simulation results show that the SRAM cell can provide full immunity for single node upset and multiple-node upset. And its critical charge is 25 times compared with Quatro10T. Besides, by comparing several electrical parameters, the proposed SRAM cell has the highly reliable and low-power capability for severe radiation environment application.

This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-powerdelay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.