A novel highly reliable and low-power radiation hardened SRAM bit-cell design

Abstract

In this paper, an improved SEU hardened SRAM bit-cell, based on the SEU physics mechanism and reasonable circuit-design, is proposed. The proposed SRAM cell can offer differential read operation for robust sensing. By using 90 nm standard digital CMOS technology, the simulation results show that the SRAM cell can provide full immunity for single node upset and multiple-node upset. And its critical charge is 25 times compared with Quatro10T. Besides, by comparing several electrical parameters, the proposed SRAM cell has the highly reliable and low-power capability for severe radiation environment application.

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

“…The schematic of the Lin12T cell [18] is shown in FIGURE 2-(b). The source and drain terminals of access transistors N5 and N6 connect bit lines (BL and BLN) and storage nodes (Q and QN).…”

“…Since the 6T cell cannot tolerate SEUs, many radiation hardened memory cells have been proposed to improve robustness. Typical SEU and/or even DNU hardened cells include NASA13T [17], Lin12T [18], RHD12T [19], RH12T [20], QUCCE10T [21], and QUCCE12T [21]. However, these memory cells still have the following problems.…”

“…(1) Most of the existing memory cells suffer from a large silicon area and power dissipation, such as NASA13T [17], Lin12T [18], and RH12T [20]. Moreover, some cells suffer from a large read and write access time, such as NASA13T [17] and QUCCE10T [21].…”

“…(2) Most of the existing memory cells have not been effectively hardened, since one or more nodes cannot tolerate SEUs, such as NASA13T [17]. Moreover, some memory cells cannot tolerate DNUs, such as Lin12T [18], RHD12T [19], RH12T [20], QUCCE10T [21], and QUCCE12T [21].…”

A single event upset tolerant latch with parallel nodes

“…For the ICs in spaceflight systems, when semi-conductor material is struck by the highly energetic particles that existing in the outer space, the generated carriers are likely to be gathered by the sensitive nodes. It is likely to cause voltage transients at the nodes [8,9,10,11,12,13]. If the voltage transients occur at the storage nodes of latches, the data stored might be flipped [7,14,15,16,17,18].…”