A novel self-recoverable and triple nodes upset resilience DICE latch

Abstract

With the CMOS technology scaling down, the normal latch is more susceptible to soft errors caused by radiation particles. In this paper, we proposed a low-power and highly reliable radiation hardened latch to enhance the single event upset (SEU) tolerance. Based on DICE latch and Muller C-element circuit, the proposed latch can provide 100% fault tolerance, which can be used for space applications in severe ray radiation environments. The simulation show that's it not only can completely tolerate an SEU on any one of its internal single node, but it also can provide doublenode and triple-node upsets protection for facultative initial state of the latch. What's more, compared with other hardened latches, the proposed cell has comparable or better performance in the matter of delay time and power.

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

“…This section reviews typical previous hardened latch designs, namely DET-SEHPL [19], LSEH [20], DNURL [21], THLTCH [22], TNUDICE [6], and TNUHL [5]. In these designs, some components such as CEs, STs, and DICEs are widely used, and Fig.…”

“…However, in the advanced highly-integrated nano-scale CMOS technologies, due to charge-sharing, a high-energy striking-particle can unfortunately simultaneously change the logic states of double nodes in a storage cell, resulting in a DNU. The scenario that triple nodes are simultaneously affected is called a TNU [4][5][6][7][8]. Obviously, reliability design against soft errors only targeting SNUs and/or SETs are no longer sufficient for high reliability requirements in safety-critical applications.…”

“…To mitigate SNUs, DNUs, TNUs, and/or SETs, by means of radiation-hardening-by-design (RHBD) approaches, many hardened storage cells such as static random access memories (SRAMs) [9][10][11][12], flip-flops [13][14][15][16], and latches [5][6][7][8][17][18][19][20][21][22][23][24][25][26][27], have been proposed. This paper focuses on latches.…”

A single event upset tolerant latch with parallel nodes

“…The simulation results of circuit-level performance including area, delay, and power consumption. According to references [10,14], we use the number of the transistors in the latch to represent the area of the latch. The delay is measured through calculating the delay from the input D to the output Q when the latch works in the transparent mode of operation.…”

“…For the ICs in spaceflight systems, when semi-conductor material is struck by the highly energetic particles that existing in the outer space, the generated carriers are likely to be gathered by the sensitive nodes. It is likely to cause voltage transients at the nodes [8,9,10,11,12,13]. If the voltage transients occur at the storage nodes of latches, the data stored might be flipped [7,14,15,16,17,18].…”