Achieving SLC performance with MLC flash memory

Abstract

Although the Multi-Level-Cell technique is widely adopted by flashmemory vendors to boost the chip density and to lower the cost, it results in serious performance and reliability problems. Different from the past work, a new cell programming method is proposed to not only significantly improve the chip performance but also reduce the potential bit error rate. In particular, a Single-Level-Cell-like programming style is proposed to better explore the threshold-voltage relationship to denote different Multi-Level-Cell bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in Single-Level-Cell chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming style could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for Multi-Level-Cell pages.

Faster than Flash: An In-Depth Study of System Challenges for Emerging Ultra-Low Latency SSDs

“…2) Power and Garbage Collection: disparities of the power consumption trend between NVMe SSD and ULL SSD become more notable for the write services (compared with reads). We conjecture that this is because of SLC-like-Z-NAND; SLC in practice employs much fewer steps of writes (per request) on the target flash cell, compared to MLC [17,20,67,72], which exhibits lower write latency.…”

Barrier Enabled IO Stack for Flash Storage

“…On the other hand, the time to program a Flash cell has barely improved if it has not deteriorated [21]. This is due to the adoption of the finer process (sub 10 nm) [24,36], the multi-bits per cell (MLC, TLC, and QLC) [5,10] in the endless quest for higher storage density [42]. Despite the splendid performance improvement of the Flash storage claimed by the storage vendors, the service providers have difficulty in fully utilizing the underlying high performance storage.…”

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

“…The continuous increasing demand for low‐cost and high‐density memory has driven the concept of multilevel cell (MLC) flash memory 32–38 . MLC technology allows the increment in the capacity of flash memory in a given area 32–38 .…”

“…The continuous increasing demand for low-cost and high-density memory has driven the concept of multilevel cell (MLC) flash memory. [32][33][34][35][36][37][38] MLC technology allows the increment in the capacity of flash memory in a given area. [32][33][34][35][36][37][38] As compared to single-level cell, the bit density in flash memory can be doubled or tripled.…”

“…[32][33][34][35][36][37][38] MLC technology allows the increment in the capacity of flash memory in a given area. [32][33][34][35][36][37][38] As compared to single-level cell, the bit density in flash memory can be doubled or tripled. The concept of dual charge storage layer MLC has been reported in Reference 23.…”