Reusable component IP design using refinement-based design environment

Park, Sang Gyu; Yoon, Seong Yong; Chae, Soo-Ik

doi:10.1145/1118299.1118439

Cited by 8 publications

(8 citation statements)

References 6 publications

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“…As the design complexity of digital systems grows platformbased SoC design methodologies are widely accepted [6,9,16]. With a well-defined SoC platform, complex systems can be designed in less effort and time by reusing components IPs.…”

Section: Socbase Platformmentioning

confidence: 99%

A Platform-Based SoC Design for Real-Time Stereo Vision

Yi¹,

Park²,

Kim³

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A stereo vision is able to build threedimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications

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Section: Socbase Platformmentioning

confidence: 99%

A Platform-Based SoC Design for Real-Time Stereo Vision

Yi¹,

Park²,

Kim³

2012

JSTS:Journal of Semiconductor Technology and Science

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“…We briefly introduce a template-based SoC design environment, called SoCBase-DE [3], [4], which we used in designing the VC-1 decoder. SoCBase-DE, developed by Seoul National University, is an integrated environment for both design and verification.…”

Section: Soc Design Environmentmentioning

confidence: 99%

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

Cho

Lee

Yoon

et al. 2009

IEICE Trans. Fundamentals

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SUMMARYIn this paper, we present a high-performance VC-1 mainprofile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm 2 . In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications. key words: SMPTE 421M-2006 VC-1, video decoder, transaction level modeling, design space exploration

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“…A CATtree (Communication Architecture Template Tree), which is defined for each communication primitive, is used in system function modeling and communication architecture refinement [4]. It A. Function-Level Models The CAT library in our design environment supports several types of the channels such as FIFO, array, event and variable channels.…”

Section: Communication Librarymentioning

confidence: 99%

“…For the initial communication architecture, the most of FIFO channels were refined to register-implemented FIFOs [4] with the depth enabling MB level pipelining. Decoded frame buffers were refined to a non-cached 3D array that uses an offchip SDRAM.…”

Section: Communication Refinement For H264 De-codersmentioning

confidence: 99%

Implementation of a H.264 decoder with Template-based Communication Refinement

Yoon

Park

Chae

2006

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

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We described an H.264 decoder implemented with our design methodology, in which a system function model of transaction level is first captured in SystemC and refined into RTL with a library of communication templates. We determined its communication architecture by exploring the design space with template-based communication refinement to meet its requirement of decoding VGA 30 frames per second at a clock frequency of 50MHz.

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Reusable component IP design using refinement-based design environment

Cited by 8 publications

References 6 publications

A Platform-Based SoC Design for Real-Time Stereo Vision

A Platform-Based SoC Design for Real-Time Stereo Vision

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

Implementation of a H.264 decoder with Template-based Communication Refinement

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