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Cyclopentasilane (CPS) has been studied as an liquid precursor for the deposition of thin silicon films for printed electronics and related applications. The processing involves a UV‐induced prepolymerization of CPS followed by liquid deposition and low‐temperature thermolysis. An insight into the oligomer and polymer formation including crosslinking in solution using 29Si NMR spectroscopy and electron spin resonance spectroscopy is reported. Formation of SiH (T‐units) and SiH3 (M‐units) is observed as well as short‐lived paramagnetic species. Additionally, the polymerization is followed by Raman spectroscopy. Reactive molecular dynamics simulations are applied to develop a theoretical model for the CPS‐ring‐opening and crosslinking steps. The experimental and computational data correspond well to each other and allow insight into the mechanism of polymer formation. The processing steps include spin‐coating, thermal drying, and conversion to amorphous silicon, H‐passivation, and fabrication of a CPS‐derived thin‐film transistor (TFT), without intermediate silicon crystallization. Further improvement is gained by using tetralene as a solvent, leading to a reduction of the time‐consuming polymerization step by one order of magnitude compared to cyclooctane. The overall quality and characteristics of the CPS‐derived spin‐coated silicon thin films correspond to standard plasma enhanced chemical vapor deposition‐derived devices with respect to performance levels.

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Basal Plane Dislocations (BPDs) in SiC are thought to cause degradation of bipolar diodes with blocking voltages > 2kV by triggering the formation and expansion of stacking faults during device operation. Hence, low N doped, thick epitaxial layers without BPDs are urgently needed for the realization of long-term stable SiC bipolar diodes. Such epilayers can be achieved if the conversion of the BPD into another harmless dislocation type is supported by proper epitaxial growth parameters and use of vicinal (off-cut) substrates. In this work, the influence of the substrate’s off-cut angle and of the epilayer thickness on BPD density and surface morphology were investigated. The BPD densities of epilayers grown on 2° and 4° off-cut substrates were very low compared to growth on 8° off-axis substrates. X-Ray Topography has proved that all the Threading Dislocations (TD) propagate from the substrate to the epilayer and that BPDs in the substrate convert to Threading Edge Dislocations (TED) in the epilayer, i.e. the dislocation density (DD) of the substrate determines the epilayer’s DD. The conversion of BPDs is supported by the presence of bunched steps as for growth of thick layers on 2° and 4° off-cut substrates.

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4H-SiC homoepitaxial layers free of basal plane dislocations (BPDs) are urgently needed to overcome the so-called bipolar degradation of high-voltage devices. BPDs being present in substrates are able to either propagate to the epilayer or convert to harmless threading edge dislocations (TEDs) in the epilayer. The model by Klapper predicts the conversion of BPDs to TEDs to be more efficient for growth on vicinal substrates with low off-cut angle. This paper aims to verify the model by Klapper by an extensive variation of epitaxial growth parameters and the substrates' off-cut. It is shown that the off-cut angle is the key parameter for growth of BPD-free epilayers. Furthermore, it is shown that the model also describes adequately the behavior of different types of TEDs, i.e., TED II and TED III dislocations, during epitaxial growth. Therefore, the model by Klapper is verified successfully for 4H-SiC homoepitaxial growth on vicinal substrates. V C 2013 AIP Publishing LLC. [http://dx

This manuscript presents the conceptional design of indium tin oxide inkjet inks for the manufacture of electron devices. For this purpose, the process window of the printer used is identified and the inks are conceived to meet the requirements. The nano-particles are effectively stabilized in different dispersion media. The rheological, the wetting and the drying behavior of the inks are adapted to the inkjet process and the substrates to be coated. To assemble a field effect transistor (FET), the most suitable ink is chosen and source and drain contacts are printed. In the device, a nano-particulate ZnO layer acts as semiconducting layer and the gate electrode as well as the dielectric layer is formed by a thermally oxidized silicon wafer. The electron device assembled shows the typical FET characteristic proving its functionality

The correlation of defect content and film morphology with the charge-carrier transport in field-effect devices based on zinc oxide nanoparticles was investigated. Changes in the defect content and the morphology were realized by annealing and sintering of the nanoparticle thin films. Temperature-dependent electrical measurements reveal that the carrier transport is thermally activated for both the unsintered and sintered thin films. Reduced energetic barrier heights between the particles have been determined after sintering. Additionally, the energetic barrier heights between the particles can be reduced by increasing the drain-to-source voltage and the gate-to-source voltage. The changes in the barrier height are discussed with respect to information obtained by scanning electron microscopy and photoluminescence measurements. It is found that a reduction of surface states and a lower roughness at the interface between the particle layer and the gate dielectric lead to lower barrier heights. Both surface termination and layer morphology at the interface affect the barrier height and thus are the main criteria for mobility improvement and device optimization