The IBM POWER8i processor is a 649-mm 2 , 4.2-billion transistor, high-frequency microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth shared third-level cache, and increased on and off-chip bandwidth, the POWER8 processor delivers industry-leading performance. This paper describes the circuit techniques and design methodologies that were employed for implementing this chip and that allowed it to maintain the power dissipation at the level of its predecessor while delivering a threefold increase in per-socket performance. Among the innovative technologies employed by the processor are resonant clocking, on-chip per-core voltage regulation, and enhanced eDRAM arrays.
Chip overviewThe IBM POWER8* processor [1,2] is the eighth generation of IBM Power Architecture* implemented in IBM's 22-nm embedded dynamic random access memory (eDRAM) silicon on insulator (SOI) technology [3]. The 649 mm 2 POWER8 processor die includes twelve architecturally enhanced eight-way multithreaded cores with high-throughput private second-level caches, a 96-MB high-bandwidth eDRAM third-level cache, an on-chip symmetric multi-processor (SMP) fabric, a set of cryptography and memory compression accelerators, memory controllers with I/O links capable of connecting to a maximum of eight memory buffer chips [4], six high-bandwidth off-chip SMP links, and 32 third-generation PCI Express** (PCIe**) lanes. Figure 1 shows the die photograph of the POWER8 processor. The processor cores are grouped into four quadrants. Each core has a private 512-KB level-2 (L2) cache with a read bandwidth of 64 bytes per cycle. The shared 96-MB level-3 (L3) cache is physically placed into the core quadrants. The on-chip SMP buses connecting the processor cores, memory controllers, accelerators, and I/O units are running through the horizontal stripe in the center of the chip, referred to as Fabric in Figure 1, and the vertical wiring channel in the middle. The on-node SMP buses, responsible for intra-node communication, are located along the top edge of the die, while the off-node SMP buses, responsible for inter-node communication, are located along the bottom edge together with the PCIe links. The memory links connecting the POWER8 processor to a maximum of eight memory buffer chips are located on the left and right side of the die. The accelerator units are located between the two core quadrants in the upper half of the processor die. The POWER8 processor contains approximately 4.2 billion transistors. Compared to its predecessor, the POWER7* processor [2, 5, 6], the POWER8 chip achieves a 50% improvement in single-thread performance, a two-fold increase in the per-core performance, and a three-fold increase in the chip throughput when measured at the same frequency [7]. In terms of the maximum core and SMP bus frequencies, the POWER8 processor achieves an incremental ...
