POWER5 offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in 130nm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz. General TermsDesign Keywords POWER5, Microprocessor Design, Simultaneous Multi-threading (SMT), Temperature Sensor, Power Reduction, Clock Gating POWER5 TM is the next generation of IBM's POWER microprocessors. This design, shown below in Figure 1, sets a new standard of industry-leading server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 1-64w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V.POWER5's dual-threaded SMT [1] creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised ~20% performance improvement, resizing critical micro-architectural resources almost doubles in many cases the SMT performance benefit at a 24% area cost per core.The two SMT cores interface with an enhanced memory subsystem. The cache hierarchy includes a larger (1.9MB) L2 cache, reduced L3 latency, and a larger (36MB) L3 cache located on a custom DRAM companion chip. The new on-chip main memory controller improves latency and the enhanced interconnect fabric extends SMP scalability. Figure 2 depicts the microarchitectural changes introduced with POWER5 chip.

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POWER6 TM is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-dielectric copper interconnects. The die, shown in Fig. 16.7.1, measures 341mm 2 , contains over 700M transistors, delivers clock frequencies exceeding 5GHz in high-performance applications, and consumes less than 100W in power-sensitive applications [1]. Chips with split and connected core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each, with important implications for chips with large numbers of cores. One of the power grid designs has the two processor cores on isolated logic power boundaries. The other design has both cores tied into the rest of the chip (called the nest) on both the chip and package.There are advantages and disadvantages for each of the two power grid designs. The split cores allow for independent voltagetuning optimizing power versus performance. The manufactured die has systematic and non-systematic variation across the chip that can make one core faster and have higher leakage than the other, but both cores run at the same clock frequency on POWER6. With separate power domains, the voltage can be lowered on the core with faster circuits. This is done on previous generations of PowerPC microprocessors [2]. Another advantage of split cores is supporting power down modes for an unused core. The disadvantage of the split power grid is that the cores do not benefit from being connected with the relatively quiet nest. The cores consume considerably more power and have much higher dI/dt than the nest, which is made up of mostly level-2 cache and I/O. With cores and nest connected, the cores get the benefit of sharing the quiet on-chip nest capacitance and also share a lower-inductance path to the package decoupling capacitors, further reducing power noise in the cores. Figure 16.7.2 is a simple schematic illustrating the mid-frequency characteristics of the chip and package power distribution. In the figure, R1, C1, L1, and R2 represent the package, which, for the POWER6 package, has a 125MHz resonant frequency. C2 is the intrinsic wire and device capacitance. R3 and C3 represent the added on-chip decoupling capacitance. R4 represents the (nonlinear) leakage and R5 is used to cause the current step in simulation. A single POWER6 core is capable of causing a 13W power step within about 20 clock cycles. Detailed chip-package simulation predicts this causes a 130mV power droop when the cores are split. When the cores are tied, this droop is cut in half.

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Timing uncertainty in microprocessors is comprised of several sources including PLL jitter, clock distribution skew and jitter, across chip device variations, and power supply noise. The on-chip measurement macro called SKITTER (SKew+jITTER) was designed to measure timing uncertainty from all combined sources by measuring the number of logic stages that complete in a cycle. This measure of completed delay stages has proven to be a very sensitive monitor of power supply noise, which has emerged as a dominant component of timing uncertainty. This paper describes the Skitter measurement experiences of several IBM microprocessors including PPC970MP, XBOX360 TM , CELL Broadband Engine TM , and POWER6 TM microprocessors running different workloads.

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