5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8&lt;sup&gt;TM&lt;/sup&gt; microprocessor

Toprak-Deniz, Zeynep; Sperling, Michael; Bulzacchelli, John F.; Still, Gregory; Kruse, Ryan C.; Kim, Seongwon; Boerstler, D.; Gloekler, Tilman; Robertazzi, R. P.; Stawiasz, K.; Diemoz, Timothy; English, George; Hui, David; Muench, Paul; Friedrich, Joshua

doi:10.1109/isscc.2014.6757354

Cited by 71 publications

(28 citation statements)

References 4 publications

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“…In particular, having voltage islands enables power gating, where an idle circuit block can consume zero power, as well as dynamic voltage scaling, which exploits performance-power tradeoff on the fly [26]. However, existing multiple-voltage designs typically form voltage islands at a coarse level of granularity, where an island size is at least thousands of gates.…”

Section: Dual Vddmentioning

confidence: 99%

Bridging high performance and low power in processor design

Puri

Choudhury

Qian

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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The design complexity of modern high performance processors calls for innovative design techniques and methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new processor design and optimization approaches that bridge the gap between high performance and low power. These techniques are flexible as they rely on automated synthesis-centric optimizations to enable power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor.

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Section: Dual Vddmentioning

confidence: 99%

Bridging high performance and low power in processor design

Puri

Choudhury

Qian

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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“…The need for efficient voltage regulation is more pronounced in near sub-threshold computing regime where the gate delay is highly susceptible to supply variation. An increasing number of power domains and of power states per domain, as well as decreasing decoupling capacitance per local grid and wide range of digital load currents necessitate the design of high-efficiency, compact on-die voltage regulators [5,6]. The on-chip LDO regulators are more suitable for the near-threshold/subthreshold logic circuits [7], since they can supply more stable and precise voltage with lower voltage ripple and faster transient response despite lower power efficiency, compared with the switching regulators [8], [9].Conventional Analog LDOs are not applicable at such low voltages mainly because of increase of PVT variations, poor noise characteristics and the small bias current, mainly in the sub-threshold regime [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

Maji

Ahasan

Roy

et al. 2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Abstract-On-chip voltage regulation using distributed Digital Low Drop Out (LDO) voltage regulators has been identified as a promising technique for efficient powermanagement for emerging multi-core processors. Digital LDOs (DLDO) can offer low voltage operation, faster transient response, and higher current efficiency. Response time as well as output voltage ripple can be reduced by increasing the speed of the dynamic comparators. However, the comparator offset steeply increases for high clock frequencies, thereby leading to enhanced variations in output voltage. In this work we explore the design of digital LDOs with multiple dynamic comparators that can overcome this bottleneck. In the proposed topology, we apply time-interleaved comparators with the same voltage threshold and uniform current step in order to accomplish the aforementioned features. Simulation based analysis shows that the DLDO with time-interleaved comparators can achieve better overall performance than variable step algorithm based DLDO in terms of current efficiency, ripple and settling time. For a load step of 50mA, a DLDO with 8 time-interleaved comparators could achieve an output ripple of less than 5mV, while achieving a settling time of less than 0.5us. Load current dependant dynamic adjustment of clock frequency is proposed to maintain high current efficiency of ~97%. keywords-low power, voltage regulation, VLSI, digital, circuit design

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“…To improve the power usage efficiency and control the power loss [5], many advanced techniques like leakage power reduction, aggressive active and sleep mode control, subthreshold operation [6], and dynamic voltage and frequency scaling (DVFS) [7], [8], have been widely applied in SoC products. For example, Intel [9], IBM [10], Manuscript received December 18, 2015. Manuscript revised January 25, 2016.…”

Section: Introductionmentioning

confidence: 99%

Cooperation between Distributed Power Modules for SoC Power Management

Huang

Lan

2016

IEICE Trans. Electron.

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SUMMARYDistributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.

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5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor

Cited by 71 publications

References 4 publications

Bridging high performance and low power in processor design

Bridging high performance and low power in processor design

Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

Cooperation between Distributed Power Modules for SoC Power Management

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