26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance

“…Adaptive techniques are proposed to minimize the impact of the variation to performance and energy [16,17,18,19,20]. The principle is to monitor the parameter (e.g., voltage droop, temperature) variations on-die before adjusting the supply voltage or clock frequency to compensate for the impact of variations.…”

“…The principle is to monitor the parameter (e.g., voltage droop, temperature) variations on-die before adjusting the supply voltage or clock frequency to compensate for the impact of variations. For example, [20] embeds analog voltage-droop monitors to direct the PLL to reduce clock frequency in response. However, these techniques require time to detect and react to the variations, thus only reducing a portion of the guard band for static variations [21].…”

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior

“…Overall, instantaneous power demand may surpass the capacity of the PDN, thus leading to a scenario where circuits become underpowered during relatively short time intervals, until the power demand decreases. In such scenario, voltage decreases to levels where correct operation cannot be preserved -often referred to as voltage droops -and actions such as decreasing operating frequency must be taken to decrease power demand and preserve correct operation [12], [28], [4]. While the effect of droops is relatively small in high-performance systems, in critical systems their impact on metrics like worstcase timing and power budgeting can be high.…”

“…For power verification, defining appropriate test cases and input vectors is critically important to identify whether (high) power peaks can occur and whether they can occur systematically [13]. Power peaks may lead to sporadic or frequent voltage droops that need lowering speed or stalling execution to preserve correctness [12], [28], [4], hence impacting timing of tasks in general, and real-time tasks in particular. For instance, power peaks may depend on the simultaneous occurrence of a number of events in cores, caches and on-chip interconnects, whose fine-grain control cannot be practically exercised.…”

Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

“…Since large-magnitude VDD droops rarely occur, the reserved voltage margin limits the performance and energy efficiency. Several adaptive circuit techniques [3][4][5][6][7][8][9][10] have been proposed to reduce the effect of VDD droops by sensing the VDD variation and adjusting the clock. The adaptive clocking system [4] eliminated the response-time limitation by selecting the delay-locked loop (DLL) clock output to adjust the clock.…”