6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

Today’s computing challenges: opportunities for computer hardware design

“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

“…Recently, a dramatic change has been made to break the ice. An amplitude modulation technique, which is called 4-level pulse-amplitude modulation (PAM-4), has been adopted in the industry ( Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ). With PAM-4, the interconnect can transmit two bits in one-bit period, which doubles the effective bandwidth over NRZ.…”

“…On the other hand, we can also make a bigger change on the architecture. In an analog-to-digital converter (ADC)-based interconnect or digital signal processing (DSP)-based interconnect ( LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 ; 2020 ; Im et al, 2020 ; Yoo et al, 2020 ; Harwood et al, 2007 ; Chen & Yang, 2010 ; Wang et al, 2018 ; Palermo et al, 2018 ), the analog front-end circuits of the receiver are replaced by a high-speed ADC, and a large fraction of the equalization and CDR stuffs are done in the digital domain. With that, an extensive equalization with dense digital logic is enabled.…”

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

“…Then the signal processing is implemented by digital circuit, including the slicers, the DFE and so on. Thus, these receivers are widely used because of their design flexibility [3,4,5,6,7,8,9,10,11,12]. However, the design process limits the speed of receivers.…”

Optimal PAM Order for Wireline Communication

“…Thus, finding the optimal PAM order for good balance between speed, power, and link budget is critically important. While PAM 2 and PAM 4 have been extensively studied in literature [9], [10], [11], [12], there is less study on analyzing performance of PAM N , where N > 4, to transfer data over high-loss, or ISI dominant channels. Augmented sensitivity to noise and jitter results in higher Bit Error Rate (BER), that calls for more complex Forward Error Correction (FEC) mechanisms, directly affecting power dissipation and latency.…”