A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

Chu, Sang-Hyeok; Bae, Woorham; Jeong, Gyu-Seob; Jang, Sungchun; Kim, Sung Woo; Joo, Jiho; Kim, Gyungock; Jeong, Deog‐Kyoon

doi:10.1109/jssc.2015.2465843

Cited by 44 publications

(28 citation statements)

References 29 publications

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“…However, it is hard to achieve high performance for classical analog CDRs in today's modern technologies [2]. Therefore, digital CDRs have become increasingly important for highspeed data communication.…”

Section: Introductionmentioning

confidence: 99%

“…The filter is also easily scalable, portable across CMOS technologies and highly adaptable. Therefore, a digital CDR is the optimal choice for a high speed receiver implemented in a deep-submicron technology and has been a major area of research interest in recent years [2]- [12].…”

Section: Introductionmentioning

confidence: 99%

“…so-called All-Digital Clock and Data Recovery (AD-CDR) circuits. ADCDRs are derived from the first All-Digital Phase Locked Loop (AD-PLL) introduced in [13] and comprise a phase detector and a digital controlled oscillator in addition to a digital loop filter [2]- [4], [14]- [18]. PLL-based CDR circuits have the advantage over alternative digital friendly CDRs that they have intrinsically a wide frequency capture range due to the ability to adapt both phase and frequency [19].…”

Section: Introductionmentioning

confidence: 99%

“…In prior work, the speed of the integral path of the digital loop filter is reduced by using demultiplexing [2], [18] or subsampling [3], [21]. However, the proportional path still runs at a high speed and due to this, these blocks had to be designed and laid out by hand, largely counteracting the advantages of a digital design which ultimately should allow automatic synthesis.…”

Section: Introductionmentioning

confidence: 99%

“…Thanks to the highly digital architecture, the active die area is very compact and only occupies 0.050 mm 2 which is significantly smaller than competing work [2]- [11]. Moreover, the power efficiency of the CDR core is 1.8 pJ/b which is also better than the state-of-the-art [2]- [11].…”

Section: Introductionmentioning

confidence: 99%

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A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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Abstract-Recently, there has been a strong drive to replace established analog circuits for multi-gigabit Clock and Data Recovery (CDR) by more digital solutions. We focused on PLLbased All-Digital CDR (AD-CDR) techniques which contain a Digital Loop Filter (DLF) and a Digital Controlled Oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low-complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050mm 2 and consumes only 46mW at 25Gb/s. This is the smallest area and lowest power consumption compared to the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic and supports a wide operating range (12.5Gb/s-25Gb/s), which is a significantly larger range compared to previous work. Finally, thanks to our digital architecture the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with most prior work, making our design truly adaptive.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%