A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-<inline-formula> <tex-math notation="LaTeX">${\rm G}_{\rm m}$ </tex-math> </inline-formula> Bias

CMOS Inverter as Analog Circuit: An Overview

“…From another qualitative viewpoint of large signal, the resistive feedback decreases the voltage swing; therefore, the output rise/fall time is reduced. References [13,40] verified the large-signal effect as well, such that the resistive feedback reduces ISI considerably compared to the conventional delay line, at the cost of increased power consumption due to the short-circuit current induced by the reduced voltage swing.…”

“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

“…From another qualitative viewpoint of large signal, the resistive feedback decreases the voltage swing; therefore, the output rise/fall time is reduced. References [13,40] verified the large-signal effect as well, such that the resistive feedback reduces ISI considerably The high-pass cut-off frequency of the AC-coupled buffer is calculated as follows. Using Miller approximation, the feedback resistance R F is translated to the input resistance of R F /(1 + A F ), where A F is the DC gain of the inverter.…”

“…In order technology where the strained silicon technique is not adopted, digital inverter has PMOS which is generally twice larger than NMOS, because we have to match the strength of PMOS and NMOS, since we assume that only one of the PMOS and NMOS is turned on at a time. However, in such analog inverter, the optimum is at around P/N ratio of unity, where we can achieve the highest g m per input capacitance [13]. Note that the PMOS and NMOS continuously run together in analog mode.…”

“…As a result, such delay cells have a lower bandwidth than an inverter, and therefore, they have usually become the main limiting factor of the maximum speed of a chip. As a remedy, [13,40,41] proposed a resistive-feedback based delay line whose delay is controlled by adjusting the feedback resistance. As we observed in (7) and Figure 9b, the feedback extends the bandwidth of an inverter.…”