Temperature fields in microdevices made from silicon-on-insulator ͑SOI͒ wafers are strongly influenced by the lateral thermal conductivity of the silicon overlayer, which is diminished by phonon scattering on the layer boundaries. This study measures the thermal conductivity of single-crystal silicon layers in SOI substrates at temperatures between 20 and 320 K using Joule heating and electrical-resistance thermometry in microfabricated structures. Data for layers of thickness between 0.4 and 1.6 m demonstrate the large reduction resulting from phonon-boundary scattering, particularly at low temperatures, and are consistent with predictions based on the phonon Boltzmann transport equation. © 1997 American Institute of Physics. ͓S0003-6951͑97͒02739-3͔Thin single-crystal silicon layers are becoming more common in microfabricated sensors, actuators, and transistors. These microdevices can be fabricated from silicon-oninsulator ͑SOI͒ substrates, which provide silicon layers of thickness between 0.05 and 10 m above a buried silicon dioxide layer. The performance and reliability of microdevices made from SOI substrates can be strongly influenced by lateral thermal conduction in the silicon layer. This is particularly important for transistors in SOI circuitry, 1 in which thermal conduction in the silicon device layer strongly reduces the peak temperature rise. 2 Microcantilevers made from SOI substrates are promising for high-density thermomechanical data storage 3,4 and have thermal response times and sensitivities governed by thermal conduction along the silicon layer. The thermal conductivity of silicon layers of submicrometer thickness may be strongly reduced by interfacial effects, although this has not been demonstrated previously.The thermal conductivity of silicon is dominated by phonon transport and, for the case of thin films, can be reduced by phonon scattering on boundaries and by imperfections related to the fabrication process. While phonon-boundary scattering is most important at low temperatures, where the mean free paths of phonons are longest, boundary scattering may also be very significant at room temperature and above in very thin silicon layers. 5 There are no data available to conclusively demonstrate this phenomenon in silicon layers of submicrometer thickness. Previous work 6-8 measured the lateral thermal conductivity of thin polysilicon layers in microsensors and reported a thermal conductivity reduction of up to 80% compared to that in bulk silicon. However, phonon scattering on grain boundaries is responsible for a large fraction of the thermal conductivity reduction in these layers, such that these data are inappropriate for the single-crystal layers in SOI substrates.This letter provides data and phonon transport analysis that quantify the impact of phonon-boundary scattering on heat conduction in crystalline silicon layers. The data are useful for thermal modeling of microdevices made from SOI substrates. Furthermore, since the purity and microstructural quality of silicon layers in SOI ...
Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, ds, to a value nearly 40 percent less than that of bulk silicon for ds = 0.42 μm. The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.
Thermal conduction in GeSbTe films strongly influences the writing energy and time for phase change memory (PCM) technology. This study measures the thermal conductivity of Ge2Sb2Te5 between 25 and 340°C for layers with thicknesses near 60, 120, and 350nm. A strong thickness dependence of the thermal conductivity is attributed to a combination of thermal boundary resistance (TBR) and microstructural imperfections. Stoichiometric variations significantly alter the phase transition temperatures but do not strongly impact the thermal conductivity at a given temperature. This work makes progress on extracting the TBR for Ge2Sb2Te5 films, which is a critical unknown parameter for PCM simulations.
Abstract-The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are ≤ 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node.
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