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Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail atspeed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and damage circuits under test. Several works have proposed methods to derive tests with lower peak and average switching activity during test response capture or during scan shifts. Some of these methods require additional hardware and modifications to the scan chains. In this paper we investigate a method to derive tests with reduced switching activity both during scan shifts and during test response captures. The method does not require additional hardware or modifications to the scan chains. The proposed method accepts a given test set and returns a test set of the same or smaller size with reduced switching activity. Experimental results on benchmark and industrial circuits are given. 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00 © 2007 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00

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As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the method.

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Of a thesis submitted in partial fulfillment of the requirements for the Doctor of Philosophy degree in Electrical and Computer Engineering in the

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