Low Shift and Capture Power Scan Tests

Abstract

Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail atspeed tests. Higher average switching activity causes higher power dissipation and chip temperature that may cause hot spots and damage circuits under test. Several works have proposed methods to derive tests with lower peak and average switching activity during test response capture or during scan shifts. Some of these methods require additional hardware and modifications to the scan chains. In this paper we investigate a method to derive tests with reduced switching activity both during scan shifts and during test response captures. The method does not require additional hardware or modifications to the scan chains. The proposed method accepts a given test set and returns a test set of the same or smaller size with reduced switching activity. Experimental results on benchmark and industrial circuits are given. 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00 © 2007 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing

“…Contrary to other papers [12], [13], [15], [16], the experimental results of this paper demonstrate IR-drop reduction. The results indicate that the proposed method to reduce launch-induced switching activity can also actually achieve the maximum IR-drop reduction.…”

“…X-identification [17], [18] does not take the distribution of X-bits into account. Even though the method [17], [18] can change the distribution by sorting the original test vectors proposed in [13], the reduction results may not be sufficient, as explained later in Sect. 3.2.…”

“…It has been found that even for a highly compacted test set, over 50% of X-bits can be identified without changing the fault coverage of the original test set [17], [18]. X-filling fills the identified X-bits with appropriate logic values in order to reduce launch-induced switching activity [12], [13], [15], [16], [26]. Since the post-ATPG X-filling only manipulates test data, it has such unique advantages as (1) no impact on test data volume, (2) no impact on circuit size, and (3) no impact on circuit timing.…”

“…X-identification [13] sorts test vectors according to their WSA (Weighted Switching Activity), and then identifies the larger number of X-bits in test vectors causing high WSA. However, it is difficult to accurately estimate the degree of IR-drop with WSA.…”

“…Cutting-edge EDA tools still need a significant amount of computation time to accurately estimate IR-drop. Therefore, X-identification [13] may not identify larger number of X-bits in test vectors causing high IR-drop…”