LPTest: a Flexible Low-Power Test Pattern Generator

Wu, Mengfan; Hu, Kaishun; Huang, Jiun-Lang

doi:10.1007/s10836-009-5115-5

Cited by 7 publications

(1 citation statement)

References 30 publications

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“…Generally, capture power reduction is achieved by modified ATPG procedures [3,31,33,38] or X-filling methods [1, 21, 24-26, 34, 36]. The reduction of capture power in critical areas is considered in [9,32,35,37].…”

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Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Eggersglüβ

2014

J Electron Test

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Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic Xfilling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.

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confidence: 99%