After producing a chip, the functional correctness of the integrated circuit has to be checked. Otherwise, products with malfunctions would be delivered to customers, which is not acceptable for any company. During this post-production test, input stimuli are applied and the correctness of the output response is monitored. These input stimuli are called test patterns. Many algorithms for Automatic Test Pattern Generation (ATPG) have been proposed in the last 30 years. However, due to the ever increasing design complexity, new techniques have to be developed that can cope with today's circuits.Classical approaches are based on backtracking over the circuit structure. They have been continuously improved by using dedicated data structures and adding more sophisticated techniques like simplification and learning. Approaches based on Boolean Satisfiability (SAT) have been proposed since the early 1980s. Comparisons to other "classical" approaches based on FAN, PODEM and the D-algorithm have shown the robustness and effectiveness of SAT-based techniques.Recently, there is a renewed interest in SAT, and many improvements to proof engines have been proposed. SAT solvers make use of learning and implication procedures. These new proof techniques led to breakthroughs in several applications, like formal hardware verification.In this book, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation of this problem as a SAT problem is considered. Modern SAT solvers are explained and the transformation of ATPG to SAT is discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, use of various fault models and v vi PREFACE detailed experiments on multi-million gate designs. The book describes the state-of-the-art in the field, highlights research aspects and shows directions for future work.
Abstract-AutomaticTest Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible -especially for untestable faults This paper presents a preprocessing technique that accelerates the classification of untestable faults. Those occur more frequently with increasing design sizes in industrial practice. In order to avoid overhead on testable faults, an untestability prediction is motivated. This increases the robustness of the entire ATPG process. The efficiency of the proposed method is shown during the experiments.
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