Incremental SAT Instance Generation for SAT-based ATPG

Tille, Daniel; Drechsler, Rolf

doi:10.1109/ddecs.2008.4538759

Cited by 7 publications

(8 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Finding a test pattern, however, is often more complex [33]. This is due to the stopping criterion of modern SAT solvers.…”

Section: A Sat-based Atpgmentioning

confidence: 99%

“…After the classification, the CNF is completely discarded. Therefore, the circuit-to-CNF conversion has to be done for each single target fault and consumes a large part of the overall runtime as already stated in [26], [33].…”

Section: B Circuit-to-cnf Conversionmentioning

confidence: 99%

“…It has been shown in [26], [33] that the time needed to generate an instance often exceeds the time needed to solve it. The instance generation step would be unnecessary if a circuit-based SAT solver [25], [37] is used.…”

Section: B Circuit-to-cnf Conversionmentioning

confidence: 99%

See 2 more Smart Citations

Structural heuristics for SAT-based ATPG

Tille

Eggersglüß

et al. 2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

Self Cite

View full text Add to dashboard Cite

Abstract-Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. The application of the Boolean satisfiability problem (SAT) to ATPG has been shown to be a robust alternative to traditional ATPG techniques. A major challenge of research in the field of SAT-based ATPG is to obtain a robust algorithm which can solve hard SAT instances reliably without slowing down easy-to-solve SAT instances. This is particular important, since easy-to-solve SAT instances form the majority of an ATPG run. This paper proposes two structural heuristics. The first one uses testability measurements to obtain an improved initial variable order, while the second heuristic prunes many easy-to-test faults by finding easy-to-control paths. Experimental results on large industrial designs confirm that the proposed methodologies result in a significant overall speed-up.

show abstract

“…Finding a test pattern, however, is often more complex [33]. This is due to the stopping criterion of modern SAT solvers.…”

Section: A Sat-based Atpgmentioning

confidence: 99%

Section: B Circuit-to-cnf Conversionmentioning

confidence: 99%

See 1 more Smart Citation

Structural heuristics for SAT-based ATPG

Tille

Eggersglüß

et al. 2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

Self Cite

View full text Add to dashboard Cite

show abstract

“…In [15] a detailed run time analysis of state-of-the-art SAT-based ATPG algorithms applied to industrial circuits is given. The two basic steps -SAT instance generation and solving -are compared with respect to their run time.…”

Section: Incremental Instance Generationmentioning

confidence: 99%

“…[9], [10], [6], [3]) work on an instance representation in Conjunctive Normal Form (CNF), a new SAT instance has to be generated for each fault 1 . In [15], it was shown that the run time needed for instance generation is a significant part of the overall run time and often even dominates it. Especially CNFs of untestable faults can mostly be solved very easily, because in industrial circuits the reason for the conflict is often bounded locally.…”

Section: Introductionmentioning

confidence: 99%

A fast untestability proof for SAT-based ATPG

Tille

Drechsler

2009

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

Self Cite

View full text Add to dashboard Cite

Abstract-AutomaticTest Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible -especially for untestable faults This paper presents a preprocessing technique that accelerates the classification of untestable faults. Those occur more frequently with increasing design sizes in industrial practice. In order to avoid overhead on testable faults, an untestability prediction is motivated. This increases the robustness of the entire ATPG process. The efficiency of the proposed method is shown during the experiments.

show abstract