ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Abstract

As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observation points to aid compression by reducing pattern count and data volume. Experimental results presented for industrial circuits demonstrate the effectiveness of the method.

Design for low test pattern counts

“…The basic data regarding the designs, such as the number of gates, number of scan cells, scan architecture, EDT input/output interface, and input compression, are listed in Table 1. In all experiments, observation points were inserted by deploying the state-of-the-art method presented in [15]. For each test case, horizontal conflicts were identified first, and results of this analysis have guided the process of test point insertion, as presented in Section 3.…”

“…Identification of potential test point candidates is always a complex problem because of several interacting factors. In general, optimal TPI for circuits with reconvergent fan-outs is an NP-complete problem [4] and, hence, numerous empirical guidelines and approximate techniques have been proposed [6], [7], [13], [15], [18], [20], [21] to identify suitable CP and OP locations and improve the overall circuit testability. Depending on how a test point is driven or observed, its insertion may require a few extra gates and wires routed to or from additional flip-flops to be included in scan chains.…”

Design for test methods to reduce test set size

“…Typically, these methods try to maximize the number of faults detected by a generated test. The second class of procedures insert test points to reduce pattern counts [39], [40], [41], [44], [46], [47]. Postprocessing may be used to further reduce pattern counts by eliminating redundant tests in the test sets generated by the ATPGs [28], [32], [33], [34], [35].…”

“…Several empirical methods for testability measurements have been proposed to guide test point placement [39], [40], [41], [42], [43], [44]. Circuit testability is estimated either through exact fault simulation or approximate measures.…”

“…Although testability-based TPI techniques are found to have an incidental decrease in pattern counts [23], [46], their performance in pattern count reduction is significantly less predictable. Several methods, introduced in [39], [40], [41], [44], [46], [47], focus on using test points for the purpose of test compaction. These methods model one or more aspects that determine the final test pattern count and improve test compaction results with properly inserted test points.…”