Design for low test pattern counts

Abstract

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflictreducing test points (CRTP) to significantly reduce the ATPGproduced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.