This paper presents a sequential test generation method based o n Boolean satisfiability. The method produces near-minimal test sizes. W e discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.
This paper describes a highly accurate and e cient fault simulator for interconnect opens in combinational or full-scan digital CMOS circuits. The analog behavior of the wires with interconnect opens are modeled very e ciently in the vicinity of the defect in order to predict what logic levels the fanout gates will interpret, and whether a su cient IDDQ current will be owing inside the fanout gates. The fault simulation method is based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four di erent factors that can a ect the voltage of an open into account; and considering the potential oscillation and sequential behavior of interconnect opens. The tool can simulate test vectors for both voltage and current measurements. Simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets are presented.
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