On low power test and DFT techniques for test set compaction

Remersaro, S.

doi:10.17077/etd.2bph30y6

DOI: 10.17077/etd.2bph30y6

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On low power test and DFT techniques for test set compaction

S. Remersaro¹

Abstract: Of a thesis submitted in partial fulfillment of the requirements for the Doctor of Philosophy degree in Electrical and Computer Engineering in the

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Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults

Jha¹

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With rapid advancement in science and technology and decreasing feature size of transistors, the complexity of VLSI designs is constantly increasing. With increasing density and complexity of the designs, the probability of occurrence of defects also increases. Therefore testing of designs becomes essential in order to guarantee fault-free operation of devices. vi TABLE OF CONTENTS LIST OF TABLES .

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Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults

Jha¹

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On low power test and DFT techniques for test set compaction

Abstract: Of a thesis submitted in partial fulfillment of the requirements for the Doctor of Philosophy degree in Electrical and Computer Engineering in the

Cited by 1 publication

References 75 publications

Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults

Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults

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