Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment

“…As forward implications and backward justifications are extensively used in their method, the computational complexity of this technique is quite high. To address this problem, Remersaro et al [12] developed an efficient probability-based X-filling technique, namely preferred fill, which tries to fill all X-bits in one step, based on the probability information of corresponding response. The above works try to reduce capture power consumption as much as possible.…”

“…To reduce test power in shift mode, various techniques have been proposed in the literature, in which design-for-testability (DfT) based methods such as scan chain partitioning technique [13,19] are very effective. For capture power reduction, however, there are no such effective DfT-based methods and we mainly resort to low-power X-filling techniques (e.g., [12,18,21]) to reduce switching activities in capture mode.…”

A novel X-filling method for capture power reduction

“…This paper proposes a X-filling method to reduce the capture power. Several X-filling methods have been studied to reduce capture power by controlling X-bits [6,7,8,9,10]. Justification based X-filling methods were proposed in [6,7].…”

“…Although the methods find the exact solution by pattern justification, complex gate level analysis is required for each pattern. Probability based method was proposed in [8]. It calculates the probability to take 0 or 1, and fills X-bits with a value which has the higher probability.…”

“…However, to calculate the probability, the accurate structure of the circuit under test is needed. Therefore, [6,7,8] cannot be applied to circuits of which the exact structures are unknown [7].…”