X-ray exposure during radiologically guided interventional procedures may have some deleterious effects. The aim of our study was to analyse the factors affecting patient dose during percutaneous coronary angioplasty (PTCA). We evaluated radiation dose during coronary angiography followed by one-vessel PTCA in 402 consecutive patients who were treated by three experienced physicians using both femoral and radial techniques. Fluoroscopy time (t) and patient dose measured by a dose-area product (DAP) meter were recorded. A good correlation was observed between t and the DAP (r=0.78, p<0.001). To assess the factors affecting radiation exposure, we studied the differences between operators, arterial catheterization access and stenting strategy. Median (25th to 75th percentiles) values for t were 19 (13 to 26) min and for DAP were 191 (145 to 256) Gy cm(2) for operator 3 compared with t=12 (9 to 18) min and DAP=137 (91 to 208) Gy cm(2) for operator 2 (p<0.005 versus operator 3) and t=13 (9 to 17) min, and DAP=134 (93 to 190) Gy cm(2) for operator 1 (p<0.001 versus operator 3). Differences between the radial and the femoral techniques were: t=17 (13 to 24) min versus 12 (8 to 17) min, (p<0.001) and DAP=175 (128 to 246) Gy cm(2) versus 138 (93 to 197) Gy cm(2), (p<0.001). In comparison with stenting without pre-dilation, direct stenting significantly reduced t and DAP [t=12 (9 to 16) min versus 16 (11 to 22) min, (p<0.001) and DAP=130 (95 to 186) Gy cm(2) versus 163 (119 to 230) Gy cm(2), respectively, (p<0.01)]. Radiation exposure to patients and staff are strongly dependent on operators, stenting strategy and the arterial access chosen for ad hoc one-vessel PTCA.
This paper presents a low-power and high-throughput Deblocking Filter (DBF) hardware architecture for the High Efficiency Video Coding (HEVC) standard. The architecture implements the three HEVC deblocking filtering modes, namely: (i) normal filter, (ii) strong filter and (iii) chroma filter. The designed DBF architecture is able to process 64 samples per clock cycle, considering luminance and chrominance components. The architecture was described in VHDL and synthesized targeting the CMOS standard-cell TSMC 40nm library. The power results were reached with real input samples extracted from the HEVC reference software. Synthesis results show that the DBF design, when running at 124.4MHz, can reach a throughput of 60 frames per second (fps) for a 7680×4320 (8K UHD) video resolution. At this frequency, the DBF design presented a low power dissipation of 4.73mW. The presented DBF hardware surpasses all related works in terms of throughput and power dissipation and is the unique solution able to real-time processing of 8K UHD videos at 60 frames per second.
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