An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder

Zummach, Eduardo; Palau, Roberta de Carvalho Nobre; Goebel, Jones; Sampaio, Felipe; Corrêa, Guilherme; Agostini, Luciano; Porto, Marcelo

doi:10.1109/icecs49266.2020.9294930

Cited by 4 publications

(6 citation statements)

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“…Zummach et al [59]- [61] presented architectures for the CDEF and DBF in-loop filters at the decoder side. In [59], a CDEF architecture for the decoder was presented.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

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AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

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This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

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“…Zummach et al [59]- [61] presented architectures for the CDEF and DBF in-loop filters at the decoder side. In [59], a CDEF architecture for the decoder was presented.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

“…The authors reported a throughput of UHD 4K at 60 fps for both designs. In [61], a DBF architecture for the decoder was presented. The architecture implements a parallelism of 56 samples per cycle, which is enough to allow a very low frequency when processing high resolution videos.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…AV1 presents three in-loop filters: the DBF, the constrained directional enhancement filter (CDEF) and the switchable loop restoration filter (SLRF). DBF is the first filter applied and defines four FIR filters with 13, 7, 5, and 4 taps, working separately for luminance and chrominance samples [72]. The CDEF is applied after the DBF and it is a deringing filter.…”

Section: In-loop Filtersmentioning

confidence: 99%

“…The DSGF operates based on two selfguided images [32] and the SNWF consists of a 7-tap linear filter using different coefficients based on the sample characteristics. There is only one work published in the literature that presents a hardware architecture for the AV1 DBF [72]. There are also two works implementing the CDEF hardware [75], [74].…”

Section: In-loop Filtersmentioning

confidence: 99%

“…It was implemented using the 40nm TSMC library, consuming an area of 185.36 Kgates with a power dissipation of 43.29 mW. The AV1 DBF hardware architecture targeting the decoder presented in [72] reaches real-time processing of 4K UHD videos at 60fps under a frequency of 16.2 MHz. It was implemented using the 40nm TSMC library consuming an area of 39.35 Kgates with a power dissipation of 3.96 mW.…”

Section: In-loop Filtersmentioning

confidence: 99%

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Modern Video Coding: Methods, Challenges and Systems

Palau

Silveira

Domanski

et al. 2021

JICS

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With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

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