Real-Time and Low-Power HEVC Deblocking Filter Architecture Targeting 8K UHD @ 60fps Videos

Abstract

This paper presents a low-power and high-throughput Deblocking Filter (DBF) hardware architecture for the High Efficiency Video Coding (HEVC) standard. The architecture implements the three HEVC deblocking filtering modes, namely: (i) normal filter, (ii) strong filter and (iii) chroma filter. The designed DBF architecture is able to process 64 samples per clock cycle, considering luminance and chrominance components. The architecture was described in VHDL and synthesized targeting the CMOS standard-cell TSMC 40nm library. The power results were reached with real input samples extracted from the HEVC reference software. Synthesis results show that the DBF design, when running at 124.4MHz, can reach a throughput of 60 frames per second (fps) for a 7680×4320 (8K UHD) video resolution. At this frequency, the DBF design presented a low power dissipation of 4.73mW. The presented DBF hardware surpasses all related works in terms of throughput and power dissipation and is the unique solution able to real-time processing of 8K UHD videos at 60 frames per second.

Modern Video Coding: Methods, Challenges and Systems

“…Besides the increasing in the subjective video quality, the current inloop filters also increase the encoding efficiency [31]. Current encoders use more than one filter, like the deblocking filter (DBF) [14], the switchable loop restoration filter (SLRF) [32], the sample adaptive offset (SAO) [33], and others.…”

“…HEVC specifies two in-loop filters: the deblocking filter (DBF) and the sample adaptive offset (SAO), which is a deringing filter. The HEVC DBF is applied over 8x8 blocks and the filter is composed of three FIR filters: a normal filter (4 taps) and a strong filter (5 taps) for luminance and a Chrominance filter (3 taps) for chrominance [14]. The SAO filter comprises an offset derivation stage and a filtering stage.…”

“…The first stage collects required statistics information from original and reconstructed blocks and the filtering stage performs offset filtering according with the offsets and chosen filter types [33]. There are several works in the literature implementing dedicated hardware for the HEVC DBF, like [70], [31], [14], and for the HEVC SAO, like [71] and [33].…”

“…In general, the in-loop filters are designed exploring: (i) the use of parallelism, to provide the required high throughput; (ii) low-power techniques, to support battery-powered devices; (iii) the use of common sub-expression sharing, as a strategy to reduce the number of operations and area consumption; (iv) multiplierless solutions, to decrease the amount of required computational resources; and (v) dedicated memory implementations, to reduce the number of data accesses in the main memory, thus enhancing timing efficiency. Examples of these solutions are available, respectively, in [74], [75], [14], [70], and [31]. For HEVC, an example of a highly efficient DBF architecture is presented in [31].…”

“…On the other hand, some academic works detail the proposed solutions, but most of them do not support all the encoder or decoder tools. Most of them are only focused on one of these tools, like the works [11], [12], [13], [14], which employ low-power techniques, and [15], [16], [13], which use approximate computing.…”