High-Throughput CDEF Architecture for the AV1 Decoder Targeting 4K@60fps Videos

Zummach, Eduardo; Palau, Roberta de Carvalho Nobre; Goebel, Jones; Agostini, Luciano; Porto, Marcelo

doi:10.1109/lascas45839.2020.9068979

Cited by 11 publications

(7 citation statements)

References 5 publications

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“…Zummach et al [59]- [61] presented architectures for the CDEF and DBF in-loop filters at the decoder side. In [59], a CDEF architecture for the decoder was presented.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

“…Zummach et al [59]- [61] presented architectures for the CDEF and DBF in-loop filters at the decoder side. In [59], a CDEF architecture for the decoder was presented. The CDEF process is applied to each area of size 8×8 within a frame, and the architecture was designed with enough parallelism to process an 8×8 area at every three clock cycles.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

See 1 more Smart Citation

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

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This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

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“…Zummach et al [59]- [61] presented architectures for the CDEF and DBF in-loop filters at the decoder side. In [59], a CDEF architecture for the decoder was presented.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…There is only one work published in the literature that presents a hardware architecture for the AV1 DBF [72]. There are also two works implementing the CDEF hardware [75], [74]. Finally, the literature does not present works with hardware designs for the SLRF.…”

Section: In-loop Filtersmentioning

confidence: 99%

“…In general, the in-loop filters are designed exploring: (i) the use of parallelism, to provide the required high throughput; (ii) low-power techniques, to support battery-powered devices; (iii) the use of common sub-expression sharing, as a strategy to reduce the number of operations and area consumption; (iv) multiplierless solutions, to decrease the amount of required computational resources; and (v) dedicated memory implementations, to reduce the number of data accesses in the main memory, thus enhancing timing efficiency. Examples of these solutions are available, respectively, in [74], [75], [14], [70], and [31]. For HEVC, an example of a highly efficient DBF architecture is presented in [31].…”

Section: In-loop Filtersmentioning

confidence: 99%

Modern Video Coding: Methods, Challenges and Systems

Palau

Silveira

Domanski

et al. 2021

JICS

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With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

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“…Nevertheless, due to AV1 being in its infancy, there is still a gap in works proposing hardware solutions for the referred codec. Some of the works found target some specific functions of the AV1 flow, such as Intra-Prediction [24], Constrained Directional Enhancement Filter (CDEF) [25], and Motion Compensation [26]. There are also works targeting the AV1 arithmetic coding on both encoder [27], which uses proprietary tools and technology, and decoder [28,29] sides.…”

Section: Introductionmentioning

confidence: 99%

AV1 Arithmetic Encoder Design on Open-Source EDA

Bitencourt

Ramos

Bampi

2022

JICS

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With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).

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High-Throughput CDEF Architecture for the AV1 Decoder Targeting 4K@60fps Videos

Cited by 11 publications

References 5 publications

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Modern Video Coding: Methods, Challenges and Systems

AV1 Arithmetic Encoder Design on Open-Source EDA

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