Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD Videos

Zummach, Eduardo; Palau, Roberta de Carvalho Nobre; Goebel, Jones; Palomino, Daniel; Agostini, Luciano; Porto, Marcelo

doi:10.1109/iscas45731.2020.9180525

Cited by 6 publications

(7 citation statements)

References 21 publications

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“…The architecture is composed of a direction search unit, which classifies the input texture with one of eight directions, and a filtering core unit, which filters the input texture using 64 filter kernels based on the detected direction. In [60], another version of the architecture with lower parallelism was presented, this one capable of processing an area of 8×1 of the frame at every three cycles. The authors reported a throughput of UHD 4K at 60 fps for both designs.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

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This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

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Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

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“…The CDEF is a non-linear directional low pass filter [73] composed of two main tools: the direction search (DS) and the non-linear low-pass filter (NLLPF). The DS identifies each block direction and the NLLPF is a 12-tap filter where the taps are defined according to the DS direction [74]. The SLRF is applied after the CDEF and it is a deblurring filter that works over 64x64, 128x128 or 256x256 blocks [25].…”

Section: In-loop Filtersmentioning

confidence: 99%

“…There is only one work published in the literature that presents a hardware architecture for the AV1 DBF [72]. There are also two works implementing the CDEF hardware [75], [74]. Finally, the literature does not present works with hardware designs for the SLRF.…”

Section: In-loop Filtersmentioning

confidence: 99%

“…In general, the in-loop filters are designed exploring: (i) the use of parallelism, to provide the required high throughput; (ii) low-power techniques, to support battery-powered devices; (iii) the use of common sub-expression sharing, as a strategy to reduce the number of operations and area consumption; (iv) multiplierless solutions, to decrease the amount of required computational resources; and (v) dedicated memory implementations, to reduce the number of data accesses in the main memory, thus enhancing timing efficiency. Examples of these solutions are available, respectively, in [74], [75], [14], [70], and [31]. For HEVC, an example of a highly efficient DBF architecture is presented in [31].…”

Section: In-loop Filtersmentioning

confidence: 99%

“…The AV1 CDEF architecture proposed in [74] targets the decoder side and the proposed solution reaches real-time processing of 4K UHD videos at 60fps under a frequency of 93 MHz. It was implemented using the 40nm TSMC library, consuming an area of 185.36 Kgates with a power dissipation of 43.29 mW.…”

Section: In-loop Filtersmentioning

confidence: 99%

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Modern Video Coding: Methods, Challenges and Systems

Palau

Silveira

Domanski

et al. 2021

JICS

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With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

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