Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder

Palau, Roberta de Carvalho Nobre; Penny, Wagner; Goebel, Jones; Zummach, Eduardo; Corrêa, Guilherme; Porto, Marcelo; Agostini, Luciano

doi:10.1109/sbcci55532.2022.9893219

Cited by 2 publications

(5 citation statements)

References 15 publications

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“…The second paper in the literature is our previous work [31], which was used as a basis for the architecture presented in Section IV.A.…”

Section: A Ssnwf Synthesis Resultsmentioning

confidence: 99%

“…The hardware was designed focusing on a high processing rate. In order to cover different scenarios, both architectures were evaluated targeting other resolutions/frame rates, such as 4K UHD at 30 fps and FHD at 30 fps, using as a basis our previous results published in [31] and [32].…”

Section: Designed Architecturesmentioning

confidence: 99%

“…For the transform and quantization steps, no published works were found. Six works have been published focusing on the In-loop filtering stage, and five of them were developed in our previous work: [28] and [29] are solutions targeting the CDEF, [30] target the DBF filters, and [31] and [32] target the SLRF filters, respectively for the SSNWF and the DSGF. The sixth work presents a hardware design for the SSNWF targeting the encoder side [33].…”

Section: Introductionmentioning

confidence: 99%

“…The literature presents only two related works targeting the AV1 SLRF at the decoder side ( [31] and [32]), which are previous works from the authors. The main contributions presented in this paper are:…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

Palau

Penny

Viana

et al. 2023

JICS

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This paper presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self- Guided Filter (DSGF). The SLRF is the last step in the AV1 loop restoration filters, and it is used to attenuate blurring artifacts, improving the subjective video quality and the coding efficiency. The designed hardware targeted the AV1 decoderand is able to process up to 4K Ultra-High Definition (4K UHD) videos (with 3840x2160 pixels) at 60 frames per second (fps) in real-time. In order to cover different scenarios, two other target throughputs were also evaluated: 4K UHD at 30fps and Full HD (FHD) (with 1920x1080 pixels) at 30fps. The architectures were synthesized for standard cells using the 40 nm TSMC library. The SSNWF and DSGF architectures used 37.38 Kgates and 177.58 kgates in all evaluated scenarios. Depending on the evaluated scenario, the SSNWF power dissipation varied from 8.25mWto 26.95mWand the DSGF power varied from 57.19 mW to 115.02 mW. This is the first paper in the literature presenting a hardware design for the AV1 SLRF with its two filters.

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“…The second paper in the literature is our previous work [31], which was used as a basis for the architecture presented in Section IV.A.…”

Section: A Ssnwf Synthesis Resultsmentioning

confidence: 99%

Section: Designed Architecturesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

Palau

Penny

Viana

et al. 2023

JICS

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show abstract

“…Palau, et.al [13] introduced literature presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self-Guided Filter (DSGF).…”

Section: Literature Surveymentioning

confidence: 99%

Implementation of FIR Filters through Inner product Units and Parallel Accumulations

Krishnarao,

Vandana,

Manasa

et al. 2024

TURCOMAT

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Finite Impulse Response (FIR) filters are pivotal in digital signal processing, finding applications in diverse fields like audio processing, telecommunications, and biomedical signal analysis. This work presents an enhanced implementation methodology for FIR filters utilizing inner product computation and parallel accumulations. In the existing, FIR filters are typically implemented using convolution techniques, basic adders, and multipliers, which involve sequential processing and intensive computational resources. This method often leads to latency issues and limits real-time applications. Moreover, traditional implementations suffer from inefficiencies in utilizing hardware resources optimally, leading to suboptimal performance. The proposed methodology overcomes these limitations by leveraging inner product computations and parallel accumulation techniques. By exploiting inherent parallelism in the filtering process, the proposed method significantly reduces latency and enhances throughput.

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Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder

Cited by 2 publications

References 15 publications

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

Implementation of FIR Filters through Inner product Units and Parallel Accumulations

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