Overcoming the difficulty in the precise definition of the metal phase of metal−Si heterostructures is among the key prerequisites to enable reproducible next-generation nanoelectronic, optoelectronic, and quantum devices. Here, we report on the formation of monolithic Al−Si heterostructures obtained from both bottom-up and top-down fabricated Si nanostructures and Al contacts. This is enabled by a thermally induced Al−Si exchange reaction, which forms abrupt and void-free metal−semiconductor interfaces in contrast to their bulk counterparts. The selective and controllable transformation of Si NWs into Al provides a nanodevice fabrication platform with high-quality monolithic and single-crystalline Al contacts, revealing resistivities as low as ρ = (6.31 ± 1.17) × 10 −8 Ω m and breakdown current densities of J max = (1 ± 0.13) × 10 12 Ω m −2 . Combining transmission electron microscopy and energy-dispersive X-ray spectroscopy confirmed the composition as well as the crystalline nature of the presented Al−Si−Al heterostructures, with no intermetallic phases formed during the exchange process in contrast to state-of-the-art metal silicides. The thereof formed single-element Al contacts explain the robustness and reproducibility of the junctions. Detailed and systematic electrical characterizations carried out on back-and top-gated heterostructure devices revealed symmetric effective Schottky barriers for electrons and holes. Most importantly, fulfilling compatibility with modern complementary metal−oxide semiconductor fabrication, the proposed thermally induced Al−Si exchange reaction may give rise to the development of nextgeneration reconfigurable electronics relying on reproducible nanojunctions.

The functional diversification and adaptability of the elementary switching units of computational circuits are disruptive approaches for advancing electronics beyond the static capabilities of conventional complementary metal-oxide-semiconductor-based architectures. Thereto, in this work the onedimensional nature of monocrystalline and monolithic Al−Gebased nanowire heterostructures is exploited to deliver charge carrier polarity control and furthermore to enable distinct programmable negative differential resistance at runtime. The fusion of electron and hole conduction together with negative differential resistance in a universal adaptive transistor may enable energy-efficient reconfigurable circuits with multivalued operability that are inherent components of emerging artificial intelligence electronics.

and drain electrodes in highly scaled p-channel field-effect transistors (FETs) for the realization of very-large-scale integration (VLSI) systems. [1] Despite these efforts, the continuous scaling of metaloxide-semiconductor field-effect transistors (MOSFETs) is approaching physical limits where the nature of deterministic charge carrier separation between source and drain by an energy barrier is not applicable anymore. [2,3] In the quest of overcoming scaling limitations, new lines of research arose. Device research has shifted toward new architectures, materials, and technologies to enable "More than Moore" paradigms, [4] extending the mature Si complementary metal-oxidesemiconductor (CMOS) platform. [5] In this regard, Si 1−x Ge x and Ge active regions integrated on Si platforms are promising candidates for future optoelectronic devices [6] and the realization of energy efficient steep subthreshold switches such as band-to-band tunneling transistors (TFETs), [7,8] negative capacitance Ge nanowire FETs, [9,10] and positive feedback FETs. [11] Conventionally, degenerately doped semiconductor regions in combination with thin layers made of transition-metal semiconductor alloys, such as metalsilicides [12] and metal-germanides, [13] have been used to obtain ohmic contacts to most Si 1−x Ge x and Ge based devices. Toward the achievement of ohmic contacts, pinning-free metal semiconductor contacts have been explored in Si and Ge through Si 1−x Ge x is a key material in modern complementary metal-oxide-semiconductor and bipolar devices. However, despite considerable efforts in metal-silicide and -germanide compound material systems, reliability concerns have so far hindered the implementation of metal-Si 1−x Ge x junctions that are vital for diverse emerging "More than Moore" and quantum computing paradigms. In this respect, the systematic structural and electronic properties of Al-Si 1−x Ge x heterostructures, obtained from a thermally induced exchange between ultrathin Si 1−x Ge x nanosheets and Al layers are reported. Remarkably, no intermetallic phases are found after the exchange process. Instead, abrupt, flat, and void-free junctions of high structural quality can be obtained. Interestingly, ultra-thin interfacial Si layers are formed between the metal and Si 1−x Ge x segments, explaining the morphologic stability. Integrated into omega-gated Schottky barrier transistors with the channel length being defined by the selective transformation of Si 1−x Ge x into single-elementary Al leads, a detailed analysis of the transport is conducted. In this respect, a report on a highly versatile platform with Si 1−x Ge x composition-dependent properties ranging from highly transparent contacts to distinct Schottky barriers is provided. Most notably, the presented abrupt, robust, and reliable metal-Si 1−x Ge x junctions can open up new device implementations for different types of emerging nanoelectronic, optoelectronic, and quantum devices.

In the quest to push the contemporary scientific boundaries in nanoelectronics, Ge is considered a key building block extending device performances, delivering enhanced functionalities. In this work, a quasi‐1D monocrystalline and monolithic Al–Ge–Al nanowire heterostructure are embedded into a novel field‐effect transistor architecture capable of combining Ge based electronics with an electrostatically tunable negative differential resistance (NDR) distinctly observable at room temperature. In this regard, a detailed study of the key metrics of NDR in Ge is presented. Most notably, a highly efficient and low‐footprint platform is demonstrated, paving the way for potential applications such as fast switching multi‐valued logic devices, static memory cells, or high‐frequency oscillators, all implemented in one fully complementary metal–oxide–semiconductor compatible Al‐Ge based device platform.

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

A popular approach to overcome this limitation is the course-grain reconfiguration, i.e. the signal routing to predefined logic blocks as practiced in field programmable gate arrays (FPGA). [1] This approach nevertheless leads to a high latency in data transfer and substantial chip area consumption since few active regions are not utilized at once. Distinctly, the ansatz of reconfiguration of elementary function blocks, i.e. the fine-grain reconfiguration, gives rise to a paradigm change where devices and circuits are actively redesigned after manufacturing and noteworthy even at runtime. Thereto, combinational circuits have shown benefits in area and power consumption by reconfiguration of complete logic blocks. [2] The building blocks for such circuits are RFETs, capable of merging the electrical properties of unipolar p-and n-type FETs into a single type of device with identical technology, geometry and composition. [3][4][5] Notably, RFETs do not require doping in contrast to classical FETs. Thereto, a device layout with independent gates is used to induce an additional energy barrier to the channel that blocks the undesired charge carrier type and therefore favors p-or n-type operation respectively. Consequently, reducing the technological fabrication complexity, they enable dynamic programming of circuits at the device level. [3,5] Prominent applications of such RFET devices are currently arising in the area of hardware security [6] and in highly integrated combinational and sequential logic. [5,7] Different channel materials have been employed to realize RFETs. With the use of Si channels and Ni x Si 1-x contacts various concepts with two or more independent gates have been proven experimentally. [8][9][10][11] Remarkably, symmetry in the output characteristics of p-and n-operation has been reached by the use of strain engineering both on bottom-up [12] and top-down Si nanowire RFETs [13] . Despite those outstanding efforts it has been noted, that the enhancement of the drive current and the reduction of dynamic power consumption strongly scales with the reduction of the respective Schottky barrier heights for electrons and holes. In this sense, Ge and SiGe have been identified as promising channel materials due to their reduced bandgap compared to the one of Si. Since the highest fraction of transport relevant for device and circuit performance is dictated by quantum mechanical tunneling of charge carriers [12] the use of Ge and Si x Ge 1-x channels Conventional field-effect transistor (FET) concepts are limited to static electrical functions and demand extraordinarily steep and reproducible doping concentration gradients. Reaching the physical limits of scaling, doping-free reconfigurable field-effect transistors (RFETs) capable of dynamically altering the device operation between p-or n-type, even during runtime, are emerging device concepts. In this respect, Ge has been identified as a promising channel material to enable reduction of power consumption and switching delay of RFETs. Nevertheless, its us...

Recent advances in nanoscale optoelectronic Ge devices have exposed their enormous potential for highly sensitive visible and near-infrared CMOS compatible photodetectors. In this respect, Ge nanowires, due to their nanocylinder resonator shape, have established themselves as a promising platform to significantly enhance the performance of photodetectors. Here, we present a highly sensitive polarity switchable Ge nanowire photodetector embedded in a monolithic and single-crystalline metal−semiconductor nanowire heterostructure. Operated in the negative differential resistance regime, effective dark current suppression up to a factor of 100 is achieved. In this configuration, a bias-switchable positive and negative photoconductance is observed and systematically analyzed. Further, a remarkably strong polarization anisotropy with a maximum TM/TE ratio of 33 was found for positive photoconductance. Most notably, presenting a Ge-based photodetector combining switchable photoconductance and effective dark current suppression may pave the way for advanced applications, including highly resolved imaging and light effect transistors.