A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

ACS Appl. Mater. Interfaces

et al. 2022

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Overcoming the difficulty in the precise definition of the metal phase of metal−Si heterostructures is among the key prerequisites to enable reproducible next-generation nanoelectronic, optoelectronic, and quantum devices. Here, we report on the formation of monolithic Al−Si heterostructures obtained from both bottom-up and top-down fabricated Si nanostructures and Al contacts. This is enabled by a thermally induced Al−Si exchange reaction, which forms abrupt and void-free metal−semiconductor interfaces in contrast to their bulk counterparts. The selective and controllable transformation of Si NWs into Al provides a nanodevice fabrication platform with high-quality monolithic and single-crystalline Al contacts, revealing resistivities as low as ρ = (6.31 ± 1.17) × 10 −8 Ω m and breakdown current densities of J max = (1 ± 0.13) × 10 12 Ω m −2 . Combining transmission electron microscopy and energy-dispersive X-ray spectroscopy confirmed the composition as well as the crystalline nature of the presented Al−Si−Al heterostructures, with no intermetallic phases formed during the exchange process in contrast to state-of-the-art metal silicides. The thereof formed single-element Al contacts explain the robustness and reproducibility of the junctions. Detailed and systematic electrical characterizations carried out on back-and top-gated heterostructure devices revealed symmetric effective Schottky barriers for electrons and holes. Most importantly, fulfilling compatibility with modern complementary metal−oxide semiconductor fabrication, the proposed thermally induced Al−Si exchange reaction may give rise to the development of nextgeneration reconfigurable electronics relying on reproducible nanojunctions.

Section: Table 1 Calculated Diffusion Coefficients Of the Al−simentioning

confidence: 95%

Monolithic and Single-Crystalline Aluminum–Silicon Heterostructures

Wind

ACS Appl. Mater. Interfaces

et al. 2022

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“…[20,21] Thereto, device concepts include Schottky barrier field effect transistors (SBFETs) with low or even negligible barrier heights, either achieved through dopant segregation [22,23] or the use of ultrathin insulator depinning interlayers [14][15][16] as well as the selective control of charge carrier type and concentration in so called reconfigurable FETs (RFETs). [24][25][26][27] The later are capable to overcome the static nature of CMOS by runtime reconfiguration of the transistor, that is, by programming the predominant charge carrier type. Beyond the use in emerging nanoelectronic devices, Si 1−x Ge x and Ge further offer an inherently strong spin-orbit coupling and the ability to host superconducting pairing correlations, providing a high potential for encoding, processing, or transmitting quantum information.…”

Section: Introductionmentioning

confidence: 99%

Composition Dependent Electrical Transport in Si_1−xGe_xNanosheets with Monolithic Single‐Elementary Al Contacts

Wind

et al. 2022

Small

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and drain electrodes in highly scaled p-channel field-effect transistors (FETs) for the realization of very-large-scale integration (VLSI) systems. [1] Despite these efforts, the continuous scaling of metaloxide-semiconductor field-effect transistors (MOSFETs) is approaching physical limits where the nature of deterministic charge carrier separation between source and drain by an energy barrier is not applicable anymore. [2,3] In the quest of overcoming scaling limitations, new lines of research arose. Device research has shifted toward new architectures, materials, and technologies to enable "More than Moore" paradigms, [4] extending the mature Si complementary metal-oxidesemiconductor (CMOS) platform. [5] In this regard, Si 1−x Ge x and Ge active regions integrated on Si platforms are promising candidates for future optoelectronic devices [6] and the realization of energy efficient steep subthreshold switches such as band-to-band tunneling transistors (TFETs), [7,8] negative capacitance Ge nanowire FETs, [9,10] and positive feedback FETs. [11] Conventionally, degenerately doped semiconductor regions in combination with thin layers made of transition-metal semiconductor alloys, such as metalsilicides [12] and metal-germanides, [13] have been used to obtain ohmic contacts to most Si 1−x Ge x and Ge based devices. Toward the achievement of ohmic contacts, pinning-free metal semiconductor contacts have been explored in Si and Ge through Si 1−x Ge x is a key material in modern complementary metal-oxide-semiconductor and bipolar devices. However, despite considerable efforts in metal-silicide and -germanide compound material systems, reliability concerns have so far hindered the implementation of metal-Si 1−x Ge x junctions that are vital for diverse emerging "More than Moore" and quantum computing paradigms. In this respect, the systematic structural and electronic properties of Al-Si 1−x Ge x heterostructures, obtained from a thermally induced exchange between ultrathin Si 1−x Ge x nanosheets and Al layers are reported. Remarkably, no intermetallic phases are found after the exchange process. Instead, abrupt, flat, and void-free junctions of high structural quality can be obtained. Interestingly, ultra-thin interfacial Si layers are formed between the metal and Si 1−x Ge x segments, explaining the morphologic stability. Integrated into omega-gated Schottky barrier transistors with the channel length being defined by the selective transformation of Si 1−x Ge x into single-elementary Al leads, a detailed analysis of the transport is conducted. In this respect, a report on a highly versatile platform with Si 1−x Ge x composition-dependent properties ranging from highly transparent contacts to distinct Schottky barriers is provided. Most notably, the presented abrupt, robust, and reliable metal-Si 1−x Ge x junctions can open up new device implementations for different types of emerging nanoelectronic, optoelectronic, and quantum devices.

“…In this respect, the most common approach is utilizing metal-semiconductor heterostructures embedded in a SBFET. [15] In this configuration, RFETs have already been fabricated based on Si, [4,8,16] Ge, [17][18][19] and also on 2D layered systems, like WSe 2 [20,21] or MoTe 2 , [22,23] and recently with black phosphorous. [24] Latest generation RFETs facilitate a device layout with three independent top-gates to induce additional energy barriers in the channel, enabling an even more effective suppression of the undesired charge carrier type and therefore favoring n-or p-type operation, respectively.…”

mentioning

confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...