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SUMMARYThis paper is adopting a new approach to investigate the capabilities of pathological mirror elements in the ideal representation of active building-blocks and shows that the voltage mirror (VM) and current mirror (CM) are the basic pathological elements. The descriptions for the floating mirror elements in the nodal admittance matrix (NAM), using infinity-variables, are derived. The descriptions for nullator and norator using infinity-variables in the NAM are shown to represent special cases from the derived descriptions of the floating VM and the CM, respectively. Hence, new representations for the nullator and norator in terms of the floating VM and CM, respectively, are obtained. A systematic procedure for the derivation of pathological configurations to ideally represent various analog signal-processing properties featured by active building-blocks is presented. This systematic approach became plausible by virtue of the versatility offered by the NAM descriptions of floating mirror elements. Novel pathological configurations ideally describing most popular signal-processing properties that involve differential or multiple single-ended signals; like conversion between differential and single-ended voltages, differential voltage conveying, current differencing, differential current conveying, and inverting current replication; are derived systematically using this procedure. The resulting pathological configurations are shown to be constructed mainly using mirror elements and hence the capabilities of the mirrors as basic pathological elements are further demonstrated. Pathological representations for some active building-blocks, using the derived pathological sections, are presented as application examples.

SUMMARYIn this paper, CCII-based gyrators are synthesized, modeled, and analyzed using the generalized symbolic framework for linear active circuits. The systematic synthesis method using admittance matrix expansion, included in the framework, is applied to generate optimized nullor-mirror descriptions for the gyrator. The resulting CCII-based circuit representations for the gyrators, obtained from mapping nullor-mirror pairs in the ideal realizations with equivalent second-generation current conveyors (CCIIs), can be classified into two topologies according to the type of the CCII terminals handling the gyrator input and output signals. In topology I, the gyrator input and output terminals are CCIIs Y -Z -terminals, whereas in topology II, the gyrator input and output terminals are CCIIs X -terminals. The parasitic components within the synthesized circuits, associated with the actual CCIIs, are modeled and included in their expanded admittance matrices. Exact non-ideal analysis for two circuits belonging to the two topologies, involving the reduction of their expanded admittance matrices to port admittance matrices, is then carried out to investigate the practical functional performance for these circuits at their ports. The non-ideal performance analysis based on the CCII actual parasitic elements indicates that, from a practical perspective, the CCII-based gyrator circuits belonging to topology I are more efficient and suitable for the gyrator applications than those belonging to topology II in terms of bandwidth and operation at high frequencies. SPICE simulations are included to demonstrate the analytical results for the comparison between the practical performances of the two circuit topologies.

SUMMARYThis paper is adopting a new approach in the systematic synthesis of CCII-based floating simulators. The synthesis procedure is based on the generalized systematic synthesis framework for active circuits using admittance matrix expansion. The resulting derived floating simulators include circuits that have been reported earlier in the literature in addition to novel floating simulators using various types of CCII. The synthesized floating simulators can be used to realize floating coils, FDNRs, and resistance and capacitance multipliers; according to the types of passive elements employed in the design. The potentials and drawbacks of every one of the synthesized circuits vary according to the design tradeoffs including complexity, number of active devices, number and values of grounded and floating passive elements, matching requirements, and tunability. SPICE simulations are presented to verify the performance of the new circuits obtained by systematic synthesis and hence demonstrate the potentials of the generalized synthesis framework in producing novel circuits with high performance.

SUMMARYThe voltage mirror-current mirror (VM-CM) pair is shown to be a universal active element. It provides two alternative realizations for the nullor. The VM-CM pair is also capable of realizing the op amp and all the four types of the current conveyors namely CCII−, CCII+, ICCII− and ICCII+ as special cases.

Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5 ps rms clock jitter. In comparison, existing architectures based on time-interleaving require 0 5 ps rms clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications. Index Terms-Baseband receivers, channel bank filters, jitter. I. INTRODUCTION I MAGINE the potential offered if electronic devices, such as computers, cell phones, digital cameras, MP3 players, flat panels, and external hard disks wirelessly connect to each other at speeds similar to the processing capabilities of modern computers. Although it is clear that advances in the semiconductor industry provide some of the tools for these ideas to become reality [millimeter-wave radio (mmWR) [1], [2], software-defined radio [3], [4], cognitive radio (CR) [5], [6], [54] and multistandard radio [4], [7]], there remain challenging issues that prevent wireless multichannel systems from coming to fruition. For instance, in applications such as power-spectral-density estimation for CRs [6], [8] and future mmWR standards, several gigahertz of bandwidth with high dynamic-range Manuscript

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Abstract. The paper presents the design of an autonomous, wheeless, mechanical snake robot that was modeled and built at Notre Dame University -Louaize. The robot is also capable of 3D motion with an ability to climb in the z-direction. The snake is made of a series links, each containing one to three high torque DC motors and a gearing system. They are connected to each other through Aluminum hollow rods that can be rotated through a 180° span. This allows the snake to move in various environments including unfriendly and cluttered ones. The front link has a proximity sensor used to map the environment. This mapping is sent to a microcontroller which controls and adapts the motion pattern of the snake. The snake can therefore choose to avoid obstacles, or climb over them if their height is within its range. The presented model is made of five links, but this number can be increased as their role is repetitive. The novel design is meant to overcome previous limitations by allowing 3D motion through electric actuators and low energy consumption.